LPC1113FHN33/302,5 NXP Semiconductors, LPC1113FHN33/302,5 Datasheet - Page 13

IC MCU LV 32BIT 24K FLAS 32VQFN

LPC1113FHN33/302,5

Manufacturer Part Number
LPC1113FHN33/302,5
Description
IC MCU LV 32BIT 24K FLAS 32VQFN
Manufacturer
NXP Semiconductors
Series
LPC1100Lr
Datasheet

Specifications of LPC1113FHN33/302,5

Featured Product
LPC1100L 32-Bit MCU
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
LPC1113
Core
ARM Cortex-M0
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART, SPI, SSP
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
42
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-5148
NXP Semiconductors
Table 4.
LPC1111_12_13_14
Product data sheet
Symbol
PIO0_0 to PIO0_11
RESET/PIO0_0
PIO0_1/CLKOUT/
CT32B0_MAT2
PIO0_2/SSEL0/
CT16B0_CAP0
PIO0_3
PIO0_4/SCL
PIO0_5/SDA
PIO0_6/SCK0
PIO0_7/CTS
PIO0_8/MISO0/
CT16B0_MAT0
PIO0_9/MOSI0/
CT16B0_MAT1
SWCLK/PIO0_10/
SCK0/CT16B0_MAT2
LPC1114 pin description table (PLCC44 package)
Pin
7
8
14
18
19
20
26
27
31
32
33
[2]
[3]
[3]
[3]
[4]
[4]
[3]
[3]
[3]
[3]
[3]
Start
logic
input
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Type Reset
I/O
I
I/O
I/O
O
O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
O
I/O
I/O
O
I
I/O
I/O
O
All information provided in this document is subject to legal disclaimers.
state
[1]
I; PU
-
I; PU
-
-
I; PU
-
-
I; PU
I; PU
-
I; PU
-
I; PU
-
I; PU
-
I; PU
-
-
I; PU
-
-
I; PU
-
-
-
Rev. 4 — 10 February 2011
Description
Port 0 — Port 0 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 0 pins depends
on the function selected through the IOCONFIG register block.
RESET — External reset input with 20 ns glitch filter. A LOW-going
pulse as short as 50 ns on this pin resets the device, causing I/O
ports and peripherals to take on their default states and processor
execution to begin at address 0.
PIO0_0 — General purpose digital input/output pin with 10 ns glitch
filter.
PIO0_1 — General purpose digital input/output pin. A LOW level on
this pin during reset starts the ISP command handler.
CLKOUT — Clockout pin.
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2 — General purpose digital input/output pin.
SSEL0 — Slave Select for SPI0.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 — General purpose digital input/output pin.
PIO0_4 — General purpose digital input/output pin (open-drain).
SCL — I
only if I
register.
PIO0_5 — General purpose digital input/output pin (open-drain).
SDA — I
if I
PIO0_6 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
PIO0_7 — General purpose digital input/output pin (high-current
output driver).
CTS — Clear To Send input for UART.
PIO0_8 — General purpose digital input/output pin.
MISO0 — Master In Slave Out for SPI0.
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9 — General purpose digital input/output pin.
MOSI0 — Master Out Slave In for SPI0.
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK — Serial wire clock.
PIO0_10 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
2
C Fast-mode Plus is selected in the I/O configuration register.
2
C Fast-mode Plus is selected in the I/O configuration
2
2
C-bus, open-drain clock input/output. High-current sink
C-bus, open-drain data input/output. High-current sink only
32-bit ARM Cortex-M0 microcontroller
LPC1111/12/13/14
© NXP B.V. 2011. All rights reserved.
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