LPC1113FHN33/302,5 NXP Semiconductors, LPC1113FHN33/302,5 Datasheet - Page 53

• Manufacturer Part Number: LPC1113FHN33/302,5
• Description: IC MCU LV 32BIT 24K FLAS 32VQFN
• Manufacturer: NXP Semiconductors
• Series: LPC1100Lr

Specifications of LPC1113FHN33/302,5

• Featured Product: LPC1100L 32-Bit MCU
• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: LPC1113
• Core: ARM Cortex-M0
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART, SPI, SSP
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5148

NXP Semiconductors
Table 18.
[1]
[2]
[3]
[4]
LPC1111_12_13_14
Product data sheet
Symbol
T
t
t
t
t
DS
DH
v(Q)
h(Q)
cy(PCLK)
T
main clock frequency f
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
T
T
T
cy(clk)
amb
cy(clk)
amb
= −40 °C to 85 °C.
= 25 °C; for normal voltage supply range: V
= (SSPCLKDIV × (1 + SCR) × CPSDVSR) / f
= 12 × T
Dynamic characteristics of SPI pins in SPI mode
Parameter
PCLK cycle time
data set-up time
data hold time
data output valid time in SPI mode
data output hold time in SPI mode
cy(PCLK)
main
.
Fig 28. SPI master timing in SPI mode
, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
SCK (CPOL = 0)
SCK (CPOL = 1)
Conditions
in SPI mode
in SPI mode
Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.
MOSI
MISO
MOSI
MISO
All information provided in this document is subject to legal disclaimers.
DD
Rev. 4 — 10 February 2011
main
= 3.3 V.
DATA VALID
DATA VALID
. The clock cycle time derived from the SPI bit rate T
t
v(Q)
[3][4]
[3][4]
[3][4]
[3][4]
DATA VALID
T
DATA VALID
cy(clk)
Min
20
0
3 × T
-
-
t
v(Q)
t
DS
DATA VALID
cy(PCLK)
DATA VALID
t
clk(H)
t
t
DH
DS
32-bit ARM Cortex-M0 microcontroller
+ 4
DATA VALID
DATA VALID
LPC1111/12/13/14
Typ
-
-
-
-
-
t
clk(L)
t
DH
t
h(Q)
Max
-
-
3 × T
2 × T
-
t
cy(PCLK)
cy(PCLK)
h(Q)
cy(clk)
© NXP B.V. 2011. All rights reserved.
is a function of the
+ 11
+ 5
CPHA = 1
CPHA = 0
002aae829
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Unit
ns
ns
ns
ns
ns