LPC1113FHN33/302,5 NXP Semiconductors, LPC1113FHN33/302,5 Datasheet - Page 37

• Manufacturer Part Number: LPC1113FHN33/302,5
• Description: IC MCU LV 32BIT 24K FLAS 32VQFN
• Manufacturer: NXP Semiconductors
• Series: LPC1100Lr

Specifications of LPC1113FHN33/302,5

• Featured Product: LPC1100L 32-Bit MCU
• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: LPC1113
• Core: ARM Cortex-M0
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART, SPI, SSP
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5148

NXP Semiconductors
LPC1111_12_13_14
Product data sheet
9.1 BOD static characteristics
9.2 Power consumption LPC111x/101/201/301
Table 9.
T
[1]
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see LPC111x user manual):
Symbol
V
amb
•
•
•
th
Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC111x
user manual.
Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block.
Configure GPIO pins as outputs using the GPIOnDIR registers.
Write 0 to all GPIOnDATA registers to drive the outputs LOW.
= 25 °C.
Parameter
threshold voltage
BOD static characteristics
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 10 February 2011
Conditions
interrupt level 0
interrupt level 1
interrupt level 2
interrupt level 3
reset level 0
reset level 1
reset level 2
reset level 3
assertion
de-assertion
assertion
de-assertion
assertion
de-assertion
assertion
de-assertion
assertion
de-assertion
assertion
de-assertion
assertion
de-assertion
assertion
de-assertion
[1]
32-bit ARM Cortex-M0 microcontroller
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LPC1111/12/13/14
Typ
1.65
1.80
2.22
2.35
2.52
2.66
2.80
2.90
1.46
1.63
2.06
2.15
2.35
2.43
2.63
2.71
© NXP B.V. 2011. All rights reserved.
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
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