LPC1113FHN33/302,5 NXP Semiconductors, LPC1113FHN33/302,5 Datasheet - Page 51

• Manufacturer Part Number: LPC1113FHN33/302,5
• Description: IC MCU LV 32BIT 24K FLAS 32VQFN
• Manufacturer: NXP Semiconductors
• Series: LPC1100Lr

Specifications of LPC1113FHN33/302,5

• Featured Product: LPC1100L 32-Bit MCU
• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: LPC1113
• Core: ARM Cortex-M0
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART, SPI, SSP
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5148

NXP Semiconductors
LPC1111_12_13_14
Product data sheet
10.5 I/O pins
10.6 I
Table 16.
T
[1]
Table 17.
T
[1]
[2]
[3]
[4]
[5]
Symbol
t
t
Symbol
f
t
t
t
t
t
2
r
f
SCL
f
LOW
HIGH
HD;DAT
SU;DAT
amb
amb
C-bus
Applies to standard port pins and RESET pin.
See the I
Parameters are valid over operating temperature range unless otherwise specified.
t
and the acknowledge.
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
V
C
HD;DAT
= −40 °C to +85 °C; 3.0 V ≤ V
= −40 °C to +85 °C.
IH
b
= total capacitance of one bus line in pF.
(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
Dynamic characteristic: I/O pins
Dynamic characteristic: I
2
C-bus specification UM10204 for details.
Parameter
SCL clock
frequency
fall time
LOW period of
the SCL clock
HIGH period of
the SCL clock
data hold time
data set-up
time
All information provided in this document is subject to legal disclaimers.
Parameter
rise time
fall time
Rev. 4 — 10 February 2011
[2]
[4][5][6][7]
[3][4][8]
[9][10]
DD
Conditions
pin
configured as
output
pin
configured as
output
≤ 3.6 V.
2
C-bus pins
Conditions
Standard-mode
Fast-mode
Fast-mode Plus
of both SDA and
SCL signals
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
[1]
[1]
32-bit ARM Cortex-M0 microcontroller
Min
3.0
2.5
LPC1111/12/13/14
Min
0
0
0
-
20 + 0.1 × C
-
4.7
1.3
0.5
4.0
0.6
0.26
0
0
0
250
100
50
Typ
-
-
b
© NXP B.V. 2011. All rights reserved.
Max
100
400
1
300
300
120
-
-
-
-
-
-
-
-
-
-
-
-
Max
5.0
5.0
Unit
kHz
kHz
MHz
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
Unit
ns
ns
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