LPC2378FBD144 NXP Semiconductors, LPC2378FBD144 Datasheet - Page 34

• Manufacturer Part Number: LPC2378FBD144
• Description: MCU 32BIT ARM7, 10/100, USB, CAN
• Manufacturer: NXP Semiconductors

Specifications of LPC2378FBD144

• Core Size: 32bit
• No. Of I/o's: 104
• Program Memory Size: 512KB
• Ram Memory Size: 58KB
• Cpu Speed: 72MHz
• Oscillator Type: External, Internal
• No. Of Timers: 4
• No. Of Pwm Channels: 6
• Digital Ic Case: RoHS Compliant
• Controller Family/series: LPC23xx
• Rohs Compliant: Yes

NXP Semiconductors
LPC2377_78
Product data sheet
7.25.4.3 Power-down mode
7.25.4.4 Deep power-down mode
7.25.4.5 Power domains
Power-down mode does everything that Sleep mode does, but also turns off the IRC
oscillator and the flash memory. This saves more power, but requires waiting for
resumption of flash operation before execution of code or data access in the flash memory
can be accomplished.
On the wake-up of Power-down mode, if the IRC was used before entering Power-down
mode, it will take IRC 60 μs to start-up. After this 4 IRC cycles will expire before the code
execution can then be resumed if the code was running from SRAM. In the meantime, the
flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 μs flash start-up
time. When it times out, access to the flash will be allowed. The customers need to
reconfigure the PLL and clock dividers accordingly.
Deep power-down mode is similar to the Power-down mode, but now the on-chip
regulator that supplies power to the internal logic is also shut off. This produces the lowest
possible power consumption without removing power from the entire chip. Since the Deep
power-down mode shuts down the on-chip logic power supply, there is no register or
memory retention, and resumption of operation involves the same activities as a full chip
reset.
If power is supplied to the LPC2377/78 during Deep power-down mode, wake-up can be
caused by the RTC Alarm interrupt or by external Reset.
While in Deep power-down mode, external device power may be removed. In this case,
the LPC2377/78 will start up when external power is restored.
Essential data may be retained through Deep power-down mode (or through complete
powering off of the chip) by storing data in the Battery RAM, as long as the external power
to the VBAT pin is maintained.
The LPC2377/78 provide two independent power domains that allow the bulk of the
device to have power removed while maintaining operation of the RTC and the battery
RAM.
On the LPC2377/78, I/O pads are powered by the 3.3 V (V
V
the CPU and most of the peripherals.
Depending on the LPC2377/78 application, a design can use two power options to
manage power consumption.
The first option assumes that power consumption is not a concern and the design ties the
V
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (V
a dedicated 3.3 V supply for the CPU (V
converter powered independently from the I/O pad ring enables shutting down of the I/O
pad power supply “on the fly”, while the CPU and peripherals stay active.
DD(DCDC)(3V3)
DD(3V3)
and V
pin powers the on-chip DC-to-DC converter which in turn provides power to
DD(DCDC)(3V3)
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 17 June 2010
pins together. This approach requires only one 3.3 V power
DD(DCDC)(3V3)
Single-chip 16-bit/32-bit microcontrollers
). Having the on-chip DC-to-DC
DD(3V3)
LPC2377/78
) pins, while the
© NXP B.V. 2010. All rights reserved.
DD(3V3)
34 of 68
) and