EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 122

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Operational Mode Descriptions
5–22
Stratix III Device Handbook, Volume 1
multiplier inputs and result can be registered independently. You can use
the pipeline registers within the DSP block to pipeline the multiplier
result, increasing the performance of the DSP block.
1
36-Bit Multiplier
You can efficiently construct a 36 × 36 multiplier using four 18 × 18
multipliers. This simplification fits conveniently into one half-DSP block,
and is implemented in the DSP block automatically by selecting the
36 × 36 mode. Stratix III devices can have up to two 36-bit multipliers per
DSP block (one 36-bit multiplier per half DSP block). The 36-bit multiplier
is also under the independent multiplier mode but uses the entire half
DSP block, including the dedicated hardware logic after the pipeline
registers to implement the 36 × 36 bit multiplication operation. This is
shown in
The 36-bit multiplier is useful for applications requiring more than 18-bit
precision; for example, for the mantissa multiplication portion of single
precision and extended single precision floating-point arithmetic
applications.
The round and saturation logic unit is supported for the 18-bit
independent multiplier mode only.
Figure
5–11.
Altera Corporation
October 2007