EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 815

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS II
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Table 1–122. EP3SE80 Row Pins Output Timing Parameters (Part 4 of 4)
Table 1–123. EP3SE80 Column Pin Delay Adders for Regional Clock
I/O Standard
Parameter
Strength
Current
12mA
16mA
Table 1–123
values that should be added to GCLK values. These adder values are
used to determine I/O timing when I/O pin is driven using regional
clock. This applies for all I/O standards supported by Stratix III devices.
Table 1–123
Regional Clock.
GCLK
GCLK
GCLK
GCLK
Industrial
Clock Parameter
PLL
PLL
—
—
—
—
Fast Model
t
t
t
t
CO
CO
CO
CO
and
specifies EP3SE80 Column Pin delay adders when using the
Stratix III Device Datasheet: DC and Switching Characteristics
Commercial
Table 1–124
1.872
0.012
1.88
0.02
Industrial Commercial
—
—
—
—
Fast Model
show EP3SE80 regional clock (RCLK) adder
V
2.854
2.846
0.093
0.101
1.1V
CCL
-2
2.915
1.460
2.911
1.456
=
Stratix III Device Handbook, Volume 2
V
3.132
3.126
0.177
0.183
1.1V
CCL
-3
=
4.709 5.268 5.589 5.427 5.684
2.419 2.733 2.804 2.767 2.727
4.702 5.260 5.581 5.419 5.676
2.412 2.725 2.796 2.759 2.719
V
1.1V
CCL
-2
3.429
3.421
0.284
0.292
V
1.1V
CCL
-4
=
=
V
1.1V
CCL
-3
3.268
3.264
0.241
0.245
V
1.1V
CCL
=
=
V
-4L
1.1V
CCL
-4
V
3.219
3.203
0.476
0.9V
0.45
=
CCL
=
V
1.1V
CCL
1–303
Units
=
-4L
ns
ns
ns
ns
V
0.9V
CCL
=
Units
ns
ns
ns
ns