EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 68

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

DSP Block Interface
Figure 3–6. M144K Row Unit Interface to Interconnect
DSP Block
Interface
3–10
Stratix III Device Handbook, Volume 1
Direct Link
Interconnects
LAB
C4 Interconnects
M144K Block to
LAB Row Interface
Block Interconnect Region
20
Row Interface Block
Stratix III device DSP block input registers can generate a shift register
that cascades down in the same DSP block column. Dedicated
connections between DSP blocks provide fast connections between the
shift register inputs to cascade the shift register chains. You can cascade
registers within multiple DSP blocks for 9-bit or 18-bit finite impulse
response (FIR) filters larger than four taps, with additional adder stages
implemented in ALMs. If the DSP block is configured as 36-bit blocks, the
adder, subtractor, or accumulator stages are implemented in ALMs. Each
DSP block can route the shift register chain out of the block to cascade
multiple columns of DSP blocks.
The DSP block is divided into four block units that interface with four
LAB rows on the left and right. You can consider each block unit as two
18-bit multipliers followed by an adder with 72 inputs and 36 outputs. A
local interconnect region is associated with each DSP block. Like a LAB,
this interconnect region can be fed with 20 direct link interconnects from
the LAB to the left or right of the DSP block in the same row. R4 and C4
routing resources can access the DSP block's local interconnect region.
Up to 14
Up to 5
M144K Block
datain_a[ ]
addressa[ ]
addressstall
rden/wren
byteena[ ]
clocken_a
clock_a
aclr
dataout_a[ ]
R4 Interconnects
Row Interface Block
Up to 10
Up to 16
M144K Block to
LAB Row Interface
Block Interconnect Region
20
C4 Interconnects
Altera Corporation
LAB
October 2007
Direct Link
Interconnects