EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 57

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
October 2007
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Clear and Preset Logic Control
LAB-wide signals control the logic for the register's clear signal. The ALM
directly supports an asynchronous clear function. You can achieve the
register preset through the Quartus II software’s NOT-gate push-back
logic option. Each LAB supports up to two clears.
Stratix III devices provide a device-wide reset pin (DEV_CLRn) that resets
all registers in the device. An option set before compilation in the
Quartus II software controls this pin. This device-wide reset overrides all
other control signals.
LAB Power Management Techniques
The following techniques are used to manage static and dynamic power
consumption within the LAB:
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Refer to the
Handbook for details on implementation.
Refer to the
Stratix III Devices
for detailed information on Stratix III programmable power capabilities.
Stratix III low-voltage devices (L ordering code suffix) offer
selectable core voltage to reduce both DC and AC power.
To save AC power, Quartus II forces all adder inputs low when ALM
adders are not in use.
Stratix III LABs operate in high-performance mode or low-power
mode. The Quartus II software automatically chooses the
appropriate mode for an LAB based on the design to optimize speed
vs. leakage trade-offs.
Clocks represent a significant portion of dynamic power
consumption due to their high switching activity and long paths. The
LAB clock that distributes a clock signal to registers within a LAB is
a significant contributor to overall clock power consumption. Each
LAB's clock and clock enable signal are linked. For example, a
combinational ALUT or register in a particular LAB using the
labclk1 signal also uses the labclkena1 signal. To disable
LAB-wide clock power consumption without disabling the entire
clock tree, use the LAB-wide clock enable to gate the LAB-wide
clock. The Quartus II software automatically promotes register-level
clock enable signals to the LAB-level. All registers within an LAB
that share a common clock and clock enable are controlled by a
shared gated clock. To take advantage of these clock enables, use a
clock enable construct in your HDL code for the registered logic.
Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
Power Optimization
Programmable Power and Temperature Sensing Diode in
chapter in volume 1 of the Stratix III Device Handbook
chapter in section 3 of the Quartus II
Stratix III Device Handbook, Volume 1
2–23