EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 53

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 2–15. LUT Register from Two Combinational Blocks
Altera Corporation
October 2007
datain(datac)
aclr
sclr
clk
LABs together automatically. For enhanced fitting, a long shared
arithmetic chain runs vertically allowing fast horizontal connections to
TriMatrix memory and DSP blocks. A shared arithmetic chain can
continue as far as a full column.
Similar to the carry chains, the top and bottom half of shared arithmetic
chains in alternate LAB columns can be bypassed. This capability allows
the shared arithmetic chain to cascade through half of the ALMs in a LAB
while leaving the other half available for narrower fan-in functionality.
Every other LAB column is top-half bypassable, while the other LAB
columns are bottom-half bypassable.
1
LUT-Register Mode
LUT-Register mode allows third register capability within an ALM. Two
internal feedback loops allow combinational ALUT1 to implement the
master latch and combinational ALUT0 to implement the slave latch
needed for the third register. The LUT register shares its clock, clock
enable, and asynchronous clear sources with the top dedicated register.
Figure 2–15
blocks within the ALM.
mode.
Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
Refer to
information on shared arithmetic chain interconnect.
shows the register constructed using two combinational
“ALM Interconnects” on page 2–22
Figure 2–16
shows the ALM in LUT-Register
Stratix III Device Handbook, Volume 1
4-input
5-input
LUT
LUT
combout
combout
sumout
sumout
for more
LUT regout
2–19