EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 816

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

I/O Timing
1–304
Stratix III Device Handbook, Volume 2
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
3.3-V LVTTL
3.3-V
LVCMOS
3.0-V LVTTL
Table 1–124. EP3SE80 Row Pin Delay Adders for Regional Clock
Table 1–125. EP3SE110 Column Pins Input Timing Parameters (Part 1 of 4)
I/O Standard
Parameter
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
Parameter
Table 1–124
Regional Clock.
EP3SE110 I/O Timing Parameters
Table 1–125
parameters for EP3SE110 for single-ended I/O standards.
Table 1–125
single-ended I/O standards.
t
t
t
t
t
t
Industrial
t
t
t
t
t
t
SU
SU
SU
SU
SU
SU
H
H
H
H
H
H
—
—
—
—
Fast Model
Industrial Commercial
specifies EP3SE110 Column Pins Input Timing parameters for
—
—
—
—
—
—
—
—
—
—
—
—
specifies EP3SE80 Row Pin delay adders when using the
through
Commercial
Fast Model
-0.081
1.742
1.705
-0.05
Table 1–128
-0.981
-0.366
-0.981
-0.366
-0.981
-0.366
1.089
0.474
1.089
0.474
1.089
0.474
-0.032 0.034
V
2.649
2.581
0.004 -0.047 0.031 -0.009
1.1V
CCL
-2
-1.425 -1.522 -1.638 -1.577 -1.964
-0.723 -0.852 -0.972 -0.914 -0.829
-1.425 -1.522 -1.638 -1.577 -1.964
-0.723 -0.852 -0.972 -0.914 -0.829
-1.425 -1.522 -1.638 -1.577 -1.964
-0.723 -0.852 -0.972 -0.914 -0.829
show the maximum I/O timing
V
1.567
0.865
1.567
0.865
1.567
0.865
1.1V
=
CCL
-2
=
V
2.785
1.1V
2.91
CCL
-3
V
1.683
1.013
1.683
1.013
1.683
1.013
1.1V
=
CCL
-3
=
V
3.186
3.041
0.118
1.1V
CCL
-4
V
1.813
1.147
1.813
1.147
1.813
1.147
1.1V
=
CCL
-4
=
V
3.048
0.073
1.1V
2.91
-4L
CCL
Altera Corporation
V
1.744
1.081
1.744
1.081
1.744
1.081
1.1V
=
CCL
November 2007
=
V
2.882
2.748
0.312
0.9V
-4L
0.23
-4L
CCL
V
2.125
0.990
2.125
0.990
2.125
0.990
0.9V
=
CCL
=
Units
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns