EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 408

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

JTAG Configuration
Figure 11–20. JTAG Configuration of Multiple Devices Using a Download Cable
Notes to
(1)
(2)
(3)
(4)
11–48
Stratix III Device Handbook, Volume 1
Pin 1
10-Pin Male Header
Download Cable
You should connect the pull-up resistor to the same supply voltage as the USB Blaster, MasterBlaster (V
ByteBlaster II, or ByteBlasterMV cable.
You should connect the nCONFIG, MSEL[2..0] pins to support a non-JTAG configuration scheme. If you only use
JTAG configuration, connect nCONFIG to V
whichever is convenient on your board.
Pin 6 of the header is a V
V
cable, this pin is a no connect. In the USB Blaster and ByteBlaster II cables, this pin is connected to nCE when it is
used for active serial programming, otherwise it is a no connect.
You must connect nCE to GND or drive it low for successful JTAG configuration.
(JTAG Mode)
CCIO
Figure
V
. Refer to the
CC
10 kΩ
(1)
V
(3)
11–20:
IO
1 kΩ
(1)
V
CC
V
CC
10 kΩ
MasterBlaster Serial/USB Communications Cable Data Sheet
V
CC
(1)
(2)
(2)
(2)
IO
reference voltage for the MasterBlaster output driver. V
You must connect the nCE pin to GND or drive it low during JTAG
configuration. In multi-device FPP, AS, and PS configuration chains, the
first device's nCE pin is connected to GND while its nCEO pin is connected
to nCE of the next device in the chain. The last device's nCE input comes
from the previous device, while its nCEO pin is left floating. In addition,
the CONF_DONE and nSTATUS signals are all shared in multi-device FPP,
AS, or PS configuration chains so the devices can enter user mode at the
same time after configuration is complete. When the CONF_DONE and
nSTATUS signals are shared among all the devices, you must configure
every device when JTAG configuration is performed.
If you only use JTAG configuration, Altera recommends that you connect
the circuitry as shown in
nSTATUS signals are isolated, so that each device can enter user mode
individually.
V
CC
10 kΩ
nSTATUS
nCONFIG
DCLK
MSEL[2..0]
nCE (4)
TRST
TDI
TMS
Stratix III Device
CONF_DONE
TCK
CC
TDO
(1)
, and MSEL[2..0] to ground. Pull DCLK either high or low,
V
V
CC
CC
10 kΩ
(1)
(2)
(2)
(2)
V
CC
Figure
10 kΩ
TDI
nSTATUS
nCONFIG
DCLK
MSEL[2..0]
nCE (4)
TRST
TMS
Stratix III Device
CONF_DONE
11–20, where each of the CONF_DONE and
TCK
TDO
(1)
V
V
CC
for this value. In the ByteBlasterMV
CC
10 kΩ
(1)
(2)
(2)
(2)
V
CC
IO
10 kΩ
TDI
nSTATUS
nCONFIG
DCLK
MSEL[2..0]
nCE (4)
TRST
should match the device's
Stratix II or Stratix II GX
TMS
Stratix III Device
Device
CONF_DONE
TCK
Altera Corporation
November 2007
TDO
(1)
V
CC
IO
10 kΩ
pin),