EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 370

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Fast Passive Parallel Configuration
Fast Passive
Parallel
Configuration
11–10
Stratix III Device Handbook, Volume 1
Fast passive parallel (FPP) configuration in Stratix III devices is designed
to meet the continuously increasing demand for faster configuration
times. Stratix III devices are designed with the capability of receiving
byte-wide configuration data per clock cycle.
pin settings when using the FPP configuration scheme.
You can perform FPP configuration of Stratix III devices using an
intelligent host, such as a MAX II device, or a microprocessor.
FPP Configuration Using a MAX II Device as an External Host
FPP configuration using compression and an external host provides the
fastest method to configure Stratix III devices. In this configuration
scheme, you can use a MAX II device as an intelligent host that controls
the transfer of configuration data from a storage device, such as flash
memory, to the target Stratix III device. You can store configuration data
in .rbf, .hex, or .ttf format. When using the MAX II devices as an
intelligent host, a design that controls the configuration process such as
fetching the data from flash memory and sending it to the device must be
stored in the MAX II device.
1
The ×4 DCLK signal does not require an additional pin and is sent on the
DCLK pin. The maximum DCLK frequency is 100 MHz, which results in a
maximum data rate of 200 Mbps. If you are not using the Stratix III
decompression or design security features, the data rate is ×8 the DCLK
frequency.
Figure 11–3
Stratix III device and a MAX II device for single device configuration.
Note to
(1)
FPP when not using the design security feature and/or
decompression enabled
FPP with the design security feature and/or
decompression enabled
Table 11–4. Stratix III MSEL Pin Settings for FPP Configuration Schemes
These modes are only supported when using a MAX II device or a microprocessor
with flash memory for configuration. In these modes, the host system must output
a DCLK that is ×4 the data rate.
Table
If you are using the Stratix III decompression and/or design
security feature, the external host must be able to send a DCLK
frequency that is ×4 the data rate.
shows the configuration interface connections between the
11–4:
Configuration Scheme
(1)
Table 11–4
MSEL2 MSEL1 MSEL0
0
0
Altera Corporation
shows the MSEL
November 2007
0
0
0
1