EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 261

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 7–26. LVPECL AC Coupled Termination
Figure 7–27. LVPECL DC Coupled Termination
Altera Corporation
November 2007
Output Buffer
Output Buffer
LVPECL
LVPECL
Differential LVPECL
In Stratix III devices, the LVPECL I/O standard is supported on input
clock pins on column and row I/O banks. LVPECL output operation is
not supported by Stratix III devices. LVDS input buffers are used to
support LVPECL input operation. AC coupling is required when
LVPECL common mode voltage of the output buffer is higher than
Stratix III LVPECL input common mode voltage.
AC coupled termination scheme. The 50-Ω resistors used at the receiver
end are external to the device.
DC-coupled LVPECL is supported if the LVPECL output common mode
voltage is within the Stratix III LVPECL input buffer specification (see
Figure
0.1 μF
0.1 μF
7–27).
Z
Z
Z
Z
O
O
O
O
= 50 Ω
= 50 Ω
= 50 Ω
= 50 Ω
V
ICM
100 Ω
Stratix III Device Handbook, Volume 1
50 Ω
50 Ω
LVPECL Input Buffer
LVPECL Input Buffer
Stratix III
Stratix III
Stratix III Device I/O Features
Figure 7–26
shows the
7–43