EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 335

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
Receiver Skew Margin for Non-DPA
Changes in system environment, such as temperature, media (cable,
connector, or PCB) loading effect, the receiver’s setup and hold times, and
internal skew, reduce the sampling window for the receiver. The timing
margin between the receiver’s clock input and the data input sampling
window is called Receiver Skew Margin (RSKM).
relationship between the RSKM and the receiver’s sampling window.
Transmit channel-to-channel skew (TCCS), RSKM, and the sampling
window specifications are used for high-speed source-synchronous
differential signals without DPA. When using DPA, these specifications
are exchanged for the simpler single DPA jitter tolerance specification.
For instance, the receiver skew is why each input with DPA selects a
different phase of the clock, thus removing the requirement for this
margin. In the timing diagram, TSW represents time for the sampling
window.
Table 9–3. Differential Bit Naming (Part 2 of 2)
Receiver Channel
Data Number
10
11
12
13
14
15
16
17
18
High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
8
9
MSB position
Internal 8-bit parallel data
103
111
119
127
135
143
63
71
79
87
95
Stratix III Device Handbook, Volume 1
LSB position
104
112
120
128
136
56
64
72
80
88
96
Figure 9–17
shows the
9–19