EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 89

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
8K×1
4K×2
2K×4
1K×8
Table 4–7. Stratix III M9K Block Mixed-Width Configuration (True Dual-Port Mode) (Part 1 of 2)
Read Port
True Dual-Port Mode
Stratix III M9K and M144K blocks support true dual-port mode.
Sometimes called bi-directional dual-port, this mode allows you to
perform any combination of two port operations: two reads, two writes,
or one read and one write at two different clock frequencies.
shows the true dual-port RAM configuration.
Figure 4–12. Stratix III True Dual-Port Memory
Note to
(1)
The widest bit configuration of the M9K and M144K blocks in true
dual-port mode is as follows:
■
■
Wider configurations are unavailable because the number of output
drivers is equivalent to the maximum bit width of the respective memory
block. Because true dual-port RAM has outputs on two ports, its
maximum width equals half of the total number of output drivers.
Table 4–7
true dual-port mode.
8K
v
v
v
v
True dual-port memory supports input/output clock mode in addition to the
independent clock mode shown.
512
4K
×
1
Figure
×
×
32-bit (
lists the possible M9K block mixed-port width configurations in
16-bit (
4–12:
4K
v
v
v
v
×
×
2
×
36-bit with parity) (M144K)
TriMatrix Embedded Memory Blocks in Stratix III Devices
18-bit with parity) (M9K)
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
rden_a
aclr_a
q_a[]
clock_a
2K
v
v
v
v
×
4
Write Port
1K
Stratix III Device Handbook, Volume 1
v
v
v
v
×
8
addressstall_b
address_b[]
byteena_b[]
Note (1)
512
data_b[ ]
clock_b
wren_b
rden_b
aclr_b
v
v
v
v
q_b[]
×
16
1K
—
—
—
—
×
9
Figure 4–12
512
—
—
—
—
×
4–15
18