EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 144

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Application Examples
5–44
Stratix III Device Handbook, Volume 1
For faster and more efficient chained cascade summation, the DSP block
can implement the chainout function in the cascade mode. This mode
uses the second-stage 44-bit adder to add the current Four-Multiplier
Adder of the half DSP block to the adjacent half DSP block of the
Four-Multiplier Adder as shown in
This scheme is possible because each half DSP block has two second-stage
adders. One of the two second-stage adders is used to add the current
Four-Multiplier Adder. The second second-stage adder takes the output
of the first second-stage adder and add it to the adjacent half DSP block
of the Four-Multiplier Adder result.
In
current Four-Multiplier Adder is shown as the chainout adder for clarity.
This scheme is used to chain and add multiple DSP blocks together. The
output of the chainout adder can be registered. The registered chainout
output can feed the lower adjacent DSP block for a chainout summation
or it can feed general FPGA routing. The chainout result can be zeroed
out by applying logic 1 on the dynamic zerochainout signal. The
zerochainout signal can also be registered.
Figure
5–22, the adder that adds the adjacent half DSP block to the
Figure
5–22.
Altera Corporation
October 2007