EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 5

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Contents
Chapter 5. DSP Blocks in Stratix III Devices
Chapter 6. Clock Networks and PLLs in Stratix III Devices
Altera Corporation
Conclusion ............................................................................................................................................ 4–24
Document Revision History ............................................................................................................... 4–25
Introduction ............................................................................................................................................ 5–1
DSP Block Overview ............................................................................................................................. 5–1
Simplified DSP Operation .................................................................................................................... 5–3
Operational Modes Overview ............................................................................................................. 5–9
DSP Block Resource Descriptions ..................................................................................................... 5–10
Operational Mode Descriptions ........................................................................................................ 5–18
Application Examples ......................................................................................................................... 5–41
Software Support ................................................................................................................................. 5–49
Conclusion ............................................................................................................................................ 5–49
Referenced Documents ....................................................................................................................... 5–49
Document Revision History ............................................................................................................... 5–50
Introduction ............................................................................................................................................ 6–1
Clock Networks in Stratix III Devices ................................................................................................. 6–1
PLLs in Stratix III Devices .................................................................................................................. 6–22
Read During Write ......................................................................................................................... 4–21
Power-Up Conditions and Memory Initialization .................................................................... 4–24
Power Management ....................................................................................................................... 4–24
Input Registers ................................................................................................................................ 5–11
Multiplier and First-Stage Adder ................................................................................................. 5–15
Pipeline Register Stage .................................................................................................................. 5–16
Second-Stage Adder ....................................................................................................................... 5–16
Round and Saturation Stage ......................................................................................................... 5–17
Second Adder and Output Registers ........................................................................................... 5–17
Independent Multiplier Modes .................................................................................................... 5–18
9-, 12- and 18-Bit Multiplier .......................................................................................................... 5–18
36-Bit Multiplier ............................................................................................................................. 5–22
Double Multiplier ........................................................................................................................... 5–23
Two-Multiplier Adder Sum Mode ............................................................................................... 5–25
18 × 18 Complex Multiply ............................................................................................................. 5–29
Four-Multiplier Adder ................................................................................................................... 5–31
Multiply Accumulate Mode ......................................................................................................... 5–33
Shift Modes ...................................................................................................................................... 5–34
Rounding and Saturation Mode ................................................................................................... 5–36
DSP Block Control Signals ............................................................................................................ 5–39
FIR Example .................................................................................................................................... 5–41
FFT Example ................................................................................................................................... 5–48
Clock Input Connections to PLLs ................................................................................................ 6–12
Clock Output Connections ............................................................................................................ 6–13
Clock Source Control for PLLs ..................................................................................................... 6–14
Clock Control Block ....................................................................................................................... 6–16
Clock Enable Signals ...................................................................................................................... 6–20
Contents
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