ISP1507BBS,118 NXP Semiconductors, ISP1507BBS,118 Datasheet - Page 14

• Manufacturer Part Number: ISP1507BBS,118
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507BBS,118

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285495118 ISP1507BBS-T

NXP Semiconductors
ISP1507A_ISP1507B_1
Product data sheet
7.9.12 REG3V3 and REG1V8
7.9.13 XTAL1 and XTAL2
7.9.14 RESET_N
7.9.15 DIR
The V
To prevent electrical overstress, it is strongly recommended that you attach a series
resistor on the V
internal charge pump. For details, see
Regulator output voltage. These supplies are used to power the ISP1507 internal digital
and analog circuits, and must not be used to power external circuits.
For correct operation of the regulator, it is recommended that you connect REG3V3 and
REG1V8 to decoupling capacitors. For examples, see
XTAL1 is the crystal input, and XTAL2 is the crystal output. The allowed frequency on the
XTAL1 pin depends on the ISP1507 product version.
If the link requires a 60 MHz clock from the ISP1507, then either a crystal must be
attached, or a clock of the same frequency must be driven into XTAL1, with XTAL2 left
floating.
If a crystal is attached, it requires external load capacitors to GND on each terminal of the
crystal. For details, see
If at any time the system wants to stop the clock on XTAL1, the link must first put the
ISP1507 into low-power mode. The clock on XTAL1 must be restarted before low-power
mode is exited.
An active LOW asynchronous reset pin that resets all circuits in the ISP1507. The
ISP1507 contains an internal power-on reset circuit, and therefore using the RESET_N
pin is optional. If RESET_N is not used, it must be connected to V
For details on using RESET_N, see
ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1507
holds DIR at LOW, causing the data bus to be an input. When DIR is LOW, the ISP1507
listens for data from the link. The ISP1507 pulls DIR to HIGH only when it has data to
send to the link, which is for one of two reasons:
The DIR pin can also be 3-stated by driving CHIP_SELECT_N to HIGH.
For details on DIR usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 .
•
•
To send USB receive data, RXCMD status updates and register read data to the link.
To block the link from driving the data bus during power-up, reset and low-power
(suspend) mode.
BUS
pin requires a capacitive load as shown in
BUS
pin (R
Rev. 01 — 19 May 2008
Section
VBUS
). R
16.
VBUS
Section
Section
must not be attached when using the ISP1507
9.3.2.
ISP1507A; ISP1507B
16.
Section
Section
ULPI HS USB OTG transceiver
16.
16.
CC(I/O)
© NXP B.V. 2008. All rights reserved.
.
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