ISP1507BBS,118 NXP Semiconductors, ISP1507BBS,118 Datasheet - Page 54

• Manufacturer Part Number: ISP1507BBS,118
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507BBS,118

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285495118 ISP1507BBS-T

NXP Semiconductors
Table 33.
Table 34.
Table 35.
Table 36.
ISP1507A_ISP1507B_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 5
4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 5
4
3
2
1
0
Symbol
-
ID_GND
SESS_END
SESS_VALID
VBUS_VALID
HOST_DISCON
Symbol
-
ID_GND_F
SESS_END_F
SESS_VALID_F Session Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
VBUS_VALID_F V
HOST_DISCON
_F
USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h,
S = 11h, C = 12h) bit allocation
USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h,
S = 11h, C = 12h) bit description
USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit allocation
USB_INTR_STAT - USB Interrupt Status register (address R = 13h) bit description
10.1.7 USB_INTR_STAT register
10.1.8 USB_INTR_L register
R/W/S/C
X
R
7
0
7
This register (see
The bits of the USB_INTR_L register are automatically set by the ISP1507 when an
unmasked change occurs on the corresponding interrupt source signal. The ISP1507 will
automatically clear all bits when the link reads this register, or when the PHY enters
low-power mode.
Description
reserved
ID Ground Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on ID_GND.
Session End Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
SESS_END.
SESS_VLD.
A_VBUS_VLD.
Host Disconnect Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
HOST_DISCON.
reserved
R/W/S/C
reserved
BUS
R
X
Description
reserved
ID Ground: Reflects the current value of the ID detector circuit.
Session End: Reflects the current value of the session end voltage comparator.
Session Valid: Reflects the current value of the session valid voltage comparator.
V
Host Disconnect: Reflects the current value of the host disconnect detector.
6
0
6
Valid Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
BUS
Valid: Reflects the current value of the V
R/W/S/C
Table
X
R
5
0
5
Rev. 01 — 19 May 2008
35) indicates the current value of the interrupt source signal.
ID_GND_F
R/W/S/C
ID_GND
R
4
1
4
0
SESS_END
R/W/S/C
SESS_
END_F
R
3
1
3
0
ISP1507A; ISP1507B
BUS
valid voltage comparator.
VALID_F
R/W/S/C
SESS_
SESS_
VALID
ULPI HS USB OTG transceiver
R
2
1
2
0
VALID_F
R/W/S/C
VBUS_
VBUS_
VALID
R
1
1
1
0
© NXP B.V. 2008. All rights reserved.
DISCON_F
R/W/S/C
DISCON
HOST_
HOST_
R
0
1
0
0
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