ISP1507BBS,118 NXP Semiconductors, ISP1507BBS,118 Datasheet - Page 9

• Manufacturer Part Number: ISP1507BBS,118
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507BBS,118

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285495118 ISP1507BBS-T

NXP Semiconductors
ISP1507A_ISP1507B_1
Product data sheet
7.4 Voltage regulator
7.5 Crystal oscillator and PLL
7.6 OTG module
For details on controlling resistor settings, see
The ISP1507 contains a built-in voltage regulator that conditions the V
inside the ISP1507. The voltage regulator:
Remark: The REG1V8 and REG3V3 pins require external decoupling capacitors. For
details, see
The ISP1507 has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock
generation.
The crystal oscillator takes a sine-wave input from an external crystal on the XTAL1 pin,
and converts it to a square wave clock for internal use. Alternatively, a square wave clock
of the same frequency can also be directly driven into the XTAL1 pin. Using an existing
square wave clock can save the cost of a crystal and also reduce the board size.
The PLL takes the square wave clock from the crystal oscillator and multiplies or divides it
into various frequencies for internal use.
The PLL produces the following frequencies, irrespective of the clock source:
This module contains several sub-blocks that provide all the functionality required by the
USB OTG specification. Specifically, it provides the following circuits:
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Differential and single-ended receivers to receive data at high-speed, full-speed and
low-speed
Squelch circuit to detect high-speed bus activity
High-speed disconnect detector
45
1.5 k pull-up resistor on DP for full-speed peripheral mode
15 k bus terminations on DP and DM for host and OTG modes
Supports input supply range of 3.0 V < V
Supplies internal circuitry with 1.8 V and 3.3 V
60 MHz clock for the ULPI interface controller
1.5 MHz for the low-speed USB data
12 MHz for the full-speed USB data
480 MHz for the high-speed USB data
Other internal frequencies for data conversion and data recovery
The ID detector to sense the ID pin of the micro-USB cable. The ID pin dictates which
device is initially configured as the host and which as the peripheral.
V
detection, SRP and HNP.
BUS
high-speed bus terminations on DP and DM for peripheral and host modes
comparators to determine the V
Section
16.
Rev. 01 — 19 May 2008
BUS
CC
ISP1507A; ISP1507B
voltage level. This is required for the V
Table
< 3.6 V
8.
ULPI HS USB OTG transceiver
CC
© NXP B.V. 2008. All rights reserved.
supply for use
BUS
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