ISP1507BBS,118 NXP Semiconductors, ISP1507BBS,118 Datasheet - Page 37

• Manufacturer Part Number: ISP1507BBS,118
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507BBS,118

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285495118 ISP1507BBS-T

NXP Semiconductors
ISP1507A_ISP1507B_1
Product data sheet
Fig 16. High-speed receive-to-transmit packet timing
CLOCK
DP or
DATA
[7:0]
STP
NXT
DIR
DM
D
N 4
DATA
D
N 3
9.9 Preamble
D
EOP
N 2
Preamble packets are headers to low-speed packets that must travel over a full-speed
bus, between a host and a hub. To enter preamble mode, the link sets
XCVRSELECT[1:0] = 11b in the FUNC_CTRL register (see
preamble mode, the ISP1507 operates just as in full-speed mode, and sends all data with
the full-speed rise time and fall time. Whenever the link transmits a USB packet in
preamble mode, the ISP1507 will automatically send a preamble header at full-speed bit
rate before sending the link packet at low-speed bit rate. The ISP1507 will ensure a
minimum gap of four full-speed bit times between the last bit of the full-speed PRE PID
and the first bit of the low-speed packet SYNC. The ISP1507 will drive a J for at least one
full-speed bit time after sending the PRE PID, after which the pull-up resistor can hold the
J state on the bus. An example transmit packet is shown in
In preamble mode, the ISP1507 can also receive low-speed packets from the full-speed
bus.
(three to eight clocks)
D
RX end delay
N 1
D
N
turnaround
USB interpacket delay (8 to 192 high-speed bit times)
Rev. 01 — 19 May 2008
link decision time (1 to 14 clocks)
IDLE
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
Figure
Section
17.
10.1.2). When in
(one to two clocks)
TXCMD
TX start delay
© NXP B.V. 2008. All rights reserved.
SYNC
D0
004aaa713
36 of 81
D1