ISP1507BBS,118 NXP Semiconductors, ISP1507BBS,118 Datasheet - Page 50

• Manufacturer Part Number: ISP1507BBS,118
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507BBS,118

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285495118 ISP1507BBS-T

NXP Semiconductors
Table 26.
ISP1507A_ISP1507B_1
Product data sheet
Bit
7
6
5
4 to 3
2
1 to 0
FUNC_CTRL - Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit
description
Symbol
-
SUSPENDM
RESET
OPMODE[1:0]
TERMSELECT Termination Select: Controls the internal 1.5 k full-speed pull-up resistor and 45
XCVRSELECT
[1:0]
10.1.3 INTF_CTRL register
The INTF_CTRL register enables alternative interfaces. All of these modes are optional
features provided for legacy link cores. Setting more than one of these fields results in
undefined behavior.
Description
reserved
Suspend LOW: Active LOW PHY suspend.
Places the PHY into low-power mode. The PHY will power down all blocks, except the
full-speed receiver, OTG comparators and ULPI interface pins.
To come out of low-power mode, the link must assert STP. The PHY will automatically clear
this bit when it exits low-power mode.
0b — Low-power mode
1b — Powered (default)
Reset: Active HIGH transceiver reset.
After the link sets this bit, the PHY will assert DIR and reset the digital core. This does not
reset the ULPI interface or the ULPI register set.
When reset is completed, the PHY will deassert DIR and automatically clear this bit, followed
by an RXCMD update to the link.
0b — Do not reset (default)
1b — Reset
The link must wait for DIR to deassert before using the ULPI bus. Does not reset the ULPI
interface or the ULPI register set.
Operation Mode: Selects the required bit-encoding style during transmit.
00b — Normal operation (default)
01b — Non-driving
10b — Disable bit-stuffing and NRZI encoding
11b — Do not automatically add SYNC and EOP when transmitting; must be used only for
high-speed packets
high-speed terminations. Control over bus resistors changes, depending on
XCVRSELECT[1:0], OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN, as shown in
Table
Transceiver Select: Selects the required transceiver speed.
00b — Enable the high-speed transceiver
01b — Enable the full-speed transceiver (default)
10b — Enable the low-speed transceiver
11b — Enable the full-speed transceiver for low-speed packets (full-speed preamble is
automatically prefixed)
8.
Table 27
Rev. 01 — 19 May 2008
provides the bit allocation of the register.
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
© NXP B.V. 2008. All rights reserved.
49 of 81