ISP1507BBS,118 NXP Semiconductors, ISP1507BBS,118 Datasheet - Page 79

• Manufacturer Part Number: ISP1507BBS,118
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507BBS,118

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285495118 ISP1507BBS-T

NXP Semiconductors
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. TXCMD byte format . . . . . . . . . . . . . . . . . . . . .26
Table 11. RXCMD byte format . . . . . . . . . . . . . . . . . . . . .26
Table 12. LINESTATE[1:0] encoding for upstream
Table 13. LINESTATE[1:0] encoding for downstream
Table 14. Encoded V
Table 15. V
Table 16. Encoded USB event signals . . . . . . . . . . . . . .30
Table 17. PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .34
Table 18. Link decision times . . . . . . . . . . . . . . . . . . . . .35
Table 19. Immediate register set overview . . . . . . . . . . .47
Table 20. Extended register set overview . . . . . . . . . . . .47
Table 21. VENDOR_ID_LOW - Vendor ID Low
Table 22. VENDOR_ID_HIGH - Vendor ID High
Table 23. PRODUCT_ID_LOW - Product ID Low
Table 24. PRODUCT_ID_HIGH - Product ID High
Table 25. FUNC_CTRL - Function Control register
Table 26. FUNC_CTRL - Function Control register
Table 27. INTF_CTRL - Interface Control register
Table 28. INTF_CTRL - Interface Control register
Table 29. OTG_CTRL - OTG Control register (address
Table 30. OTG_CTRL - OTG Control register (address
Table 31. USB_INTR_EN_R_E - USB Interrupt Enable
Table 32. USB_INTR_EN_R_E - USB Interrupt Enable
ISP1507A_ISP1507B_1
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Recommended charge pump capacitor value .12
ULPI signal description . . . . . . . . . . . . . . . . . .15
Signal mapping during low-power mode . . . . .16
Signal mapping for 6-pin serial mode . . . . . . .17
Signal mapping for 3-pin serial mode . . . . . . .18
Operating states and their corresponding
resistor settings . . . . . . . . . . . . . . . . . . . . . . . .18
OTG_CTRL register power control bits . . . . . .25
facing ports: peripheral . . . . . . . . . . . . . . . . . .27
facing ports: host . . . . . . . . . . . . . . . . . . . . . . .28
typical applications . . . . . . . . . . . . . . . . . . . . . .29
register (address R = 00h) bit description . . . .48
register (address R = 01h) bit description . . . .48
register (address R = 02h) bit description . . . .48
register (address R = 03h) bit description . . . .48
(address R = 04h to 06h, W = 04h, S = 05h,
C = 06h) bit allocation . . . . . . . . . . . . . . . . . . .48
(address R = 04h to 06h, W = 04h, S = 05h,
C = 06h) bit description . . . . . . . . . . . . . . . . . .49
(address R = 07h to 09h, W = 07h, S = 08h,
C = 09h) bit allocation . . . . . . . . . . . . . . . . . . .50
(address R = 07h to 09h, W = 07h, S = 08h,
C = 09h) bit description . . . . . . . . . . . . . . . . . .50
R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .51
R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .51
Rising Edge register (address R = 0Dh to 0Fh,
W = 0Dh, S = 0Eh, C = 0Fh) bit allocation . . . .52
Rising Edge register (address R = 0Dh to 0Fh,
W = 0Dh, S = 0Eh, C = 0Fh) bit description . .52
BUS
indicators in RXCMD required for
BUS
voltage state . . . . . . . . . . . . . .28
Rev. 01 — 19 May 2008
Table 33. USB_INTR_EN_F_E - USB Interrupt
Table 34. USB_INTR_EN_F_E - USB Interrupt Enable
Table 35. USB_INTR_STAT - USB Interrupt Status
Table 36. USB_INTR_STAT - USB Interrupt Status
Table 37. USB_INTR_L - USB Interrupt Latch register
Table 38. USB_INTR_L - USB Interrupt Latch register
Table 39. DEBUG - Debug register (address R = 15h)
Table 40. DEBUG - Debug register (address R = 15h)
Table 41. SCRATCH - Scratch register (address R =
Table 42. PWR_CTRL - Power Control register
Table 43. PWR_CTRL - Power Control register
Table 44. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 45. Recommended operating conditions . . . . . . . . 57
Table 46. Static characteristics: supply pins . . . . . . . . . . 58
Table 47. Static characteristics: digital pins . . . . . . . . . . 58
Table 48. Static characteristics: digital pin FAULT . . . . . 59
Table 49. Static characteristics: digital pin PSW_N . . . . 59
Table 50. Static characteristics: analog I/O pins
Table 51. Static characteristics: charge pump . . . . . . . . 61
Table 52. Static characteristics: V
Table 53. Static characteristics: V
Table 54. Static characteristics: ID detection circuit . . . . 62
Table 55. Static characteristics: resistor reference . . . . . 62
Table 56. Dynamic characteristics: reset and clock . . . . 64
Table 57. Dynamic characteristics: digital I/O pins . . . . . 65
Table 58. Dynamic characteristics: analog I/O pins
Table 59. Recommended bill of materials . . . . . . . . . . . . 68
Table 60. SnPb eutectic process (from J-STD-020C) . . . 74
Table 61. Lead-free process (from J-STD-020C) . . . . . . 74
Table 62. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 63. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 76
Enable Falling Edge register (address
R = 10h to 12h, W = 10h, S = 11h, C = 12h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Falling Edge register (address R = 10h to 12h,
W = 10h, S = 11h, C = 12h) bit description . . . 53
register (address R = 13h) bit allocation . . . . . 53
register (address R = 13h) bit description . . . . 53
(address R = 14h) bit allocation . . . . . . . . . . . 54
(address R = 14h) bit description . . . . . . . . . . 54
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 54
16h to 18h, W = 16h, S = 17h, C = 18h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
(address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,
C = 3Fh) bit allocation . . . . . . . . . . . . . . . . . . . 55
(address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,
C = 3Fh) bit description . . . . . . . . . . . . . . . . . . 55
(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
(DP and DM) . . . . . . . . . . . . . . . . . . . . . . . . . . 65
ISP1507A; ISP1507B
ULPI HS USB OTG transceiver
BUS
BUS
comparators . . . . 61
resistors . . . . . . . . 62
© NXP B.V. 2008. All rights reserved.
78 of 81