ISP1507BBS,118 NXP Semiconductors, ISP1507BBS,118 Datasheet - Page 32

• Manufacturer Part Number: ISP1507BBS,118
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507BBS,118

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285495118 ISP1507BBS-T

NXP Semiconductors
ISP1507A_ISP1507B_1
Product data sheet
Fig 12. Example of register write, register read, extended register write and extended register read
DATA[7:0]
CLOCK
NXT
STP
DIR
AD indicates the address byte, and D indicates the data byte.
9.6 Register read and write operations
9.7 USB reset and high-speed detection handshake (chirp)
(REGW)
register write
TXCMD
immediate
Figure 12
addressing and extended addressing register operations. Extended register addressing is
optional for links. Note that register operations will be aborted if the ISP1507 unexpectedly
asserts DIR during the operation. When a register operation is aborted, the link must retry
until successful. For more information on register operations, refer to UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1 .
Figure 13
handshake (chirp). The sequence is shown for hosts and peripherals.
show all RXCMD updates and timing is not to scale. The sequence is as follows:
1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and
2. High-speed detection handshake (chirp)
D
as full-speed if DP is HIGH. If a host detects a low-speed peripheral, it does not follow
the remainder of this protocol. If a host detects a full-speed peripheral, it resets the
peripheral by writing to the Function Control register (see
XCVRSELECT[1:0] = 00b (high-speed) and TERMSELECT = 0b are then set which
drives SE0 on the bus (DP and DM are connected to ground through 45 ). The host
also sets OPMODE[1:0] = 10b for correct chirp transmit and receive. The start of SE0
is labeled T
Remark: To receive chirp signaling, the host must also consider the high-speed
differential receiver output. The host controller must interpret LINESTATE[1:0] as
shown in
a. Peripheral chirp: After detecting SE0 for no less than 2.5 s, if the peripheral is
capable of high-speed, it sets XCVRSELECT[1:0] = 00b (high-speed) and
OPMODE[1:0] = 10b (chirp). The peripheral immediately follows this with a
TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more
shows register read and write sequences. The ISP1507 supports immediate
shows the sequence of events for USB reset and high-speed detection
TXCMD
(EXTW) AD D
register write
Table
extended
0
.
13.
Rev. 01 — 19 May 2008
TXCMD
(REGR)
register read
immediate
D
ISP1507A; ISP1507B
TXCMD
(EXTW)
register read
extended
AD
ULPI HS USB OTG transceiver
D
Section
Figure 13
10.1.2).
© NXP B.V. 2008. All rights reserved.
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does not
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