K4T1G164QF-BCE6

Manufacturer Part NumberK4T1G164QF-BCE6
ManufacturerSamsung Semiconductor
K4T1G164QF-BCE6 datasheet
 

Specifications of K4T1G164QF-BCE6

Lead Free Status / Rohs StatusCompliant  
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1Gb F-die DDR2 SDRAM
60FBGA/84FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
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ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.
- 1 -
Rev. 1.11, Sep. 2010
K4T1G044QF
K4T1G084QF
K4T1G164QF

K4T1G164QF-BCE6 Summary of contents

  • Page 1

    ... For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved Rev. 1.11, Sep. 2010 K4T1G044QF K4T1G084QF K4T1G164QF ...

  • Page 2

    ... K4T1G044QF K4T1G084QF K4T1G164QF Revision History Revision No. 1.0 - Final Spec. Release 1.1 - Changed IDD current spec.(IDD3P-S/IDD3N/IDD4W) - Corrected typo V (AC) Max. on page 14. 1.11 ID datasheet History - 2 - Rev. 1.11 DDR2 SDRAM Draft Date Remark Editor May. 2010 - S.H.Kim Aug. 2010 - S.H.Kim Sep. 2010 - S.H.Kim ...

  • Page 3

    ... K4T1G044QF K4T1G084QF K4T1G164QF Table Of Contents 1Gb F-die DDR2 SDRAM 1. Ordering Information ..................................................................................................................................................... 4 2. Key Features................................................................................................................................................................. 4 3. Package pinout/Mechanical Dimension & Addressing.................................................................................................. 5 3.1 x4 Package Pinout (Top view) : 60ball FBGA Package .......................................................................................... 5 3.2 x8 Package Pinout (Top view) : 60ball FBGA Package .......................................................................................... 6 3.3 x16 Package Pinout (Top view) : 84ball FBGA Package ........................................................................................ 7 3 ...

  • Page 4

    ... The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V V The 1Gb DDR2 device is available in 60ball FBGA(x4/x8) and in 84ball FBGA(x16). 85°C, 3.9us at CASE - 4 - DDR2 SDRAM DDR2-667 5-5-5 K4T1G044QF-BCE6 K4T1G084QF-BCE6 K4T1G164QF-BCE6 DDR2-667 5-5-5 Units DDQ Rev. 1.11 Package ...

  • Page 5

    ... K4T1G044QF K4T1G084QF K4T1G164QF 3. Package pinout/Mechanical Dimension & Addressing 3.1 x4 Package Pinout (Top view) : 60ball FBGA Package DDQ DDL F G BA2 NOTE : V and V are power and ground for the DLL recommended that they be isolated on the device from V DDL SSDL Ball Locations (x4) ...

  • Page 6

    ... K4T1G044QF K4T1G084QF K4T1G164QF 3.2 x8 Package Pinout (Top view) : 60ball FBGA Package DQ6 V C DDQ D DQ4 V E DDL F G BA2 NOTE : 1. Pins B3 and A2 have identical capacitances as pins B7 and A8. 2. For a Read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & DQS and input data masking function is disabled ...

  • Page 7

    ... K4T1G044QF K4T1G084QF K4T1G164QF 3.3 x16 Package Pinout (Top view) : 84ball FBGA Package DQ14 V C DDQ D DQ12 DQ6 V G DDQ H DQ4 V J DDL K L BA2 NOTE : V and V are power and ground for the DLL recommended that they be isolated on the device from V DDL ...

  • Page 8

    ... K4T1G044QF K4T1G084QF K4T1G164QF 3.4 FBGA Package Dimension (x4/x8) (Datum A) (Datum B) 60-∅0.48 Solder ball (Post reflow 0.50 ± 0.05) 0 #A1 datasheet 7.50 ± 0. INDEX MARK 3.20 0.80 1. (0.30) MOLDING AREA (0.60) BOTTOM VIEW 7.50 ± 0.10 TOP VIEW - 8 - Rev. 1.11 ...

  • Page 9

    ... K4T1G044QF K4T1G084QF K4T1G164QF 3.5 FBGA Package Dimension (x16) (Datum A) (Datum B) 84-∅0.48 Solder ball (Post reflow 0.50 ± 0.05) 0 #A1 datasheet 7.50 ± 0. INDEX MARK 3.20 0.80 1. (0.30) MOLDING AREA (0.60) BOTTOM VIEW 7.50 ± 0.10 TOP VIEW - 9 - Rev. 1.11 ...

  • Page 10

    ... K4T1G044QF K4T1G084QF K4T1G164QF 4. Input/Output Functional Description Symbol Type Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the CK, CK Input positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing) ...

  • Page 11

    ... K4T1G044QF K4T1G084QF K4T1G164QF 5. DDR2 SDRAM Addressing 1Gb Addressing Configuration # of Bank Bank Address Auto precharge Row Address Column Address * Reference information: The following tables are address mapping information for other densities. 256Mb Configuration # of Bank Bank Address Auto precharge Row Address Column Address ...

  • Page 12

    ... K4T1G044QF K4T1G084QF K4T1G164QF 6. Absolute Maximum Ratings Symbol Parameter Voltage on V pin relative Voltage on V pin relative DDQ DDQ Voltage on V pin relative DDL DDL Voltage on any pin relative IN, OUT T Storage Temperature STG NOTE : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...

  • Page 13

    ... K4T1G044QF K4T1G084QF K4T1G164QF 7.2 Operating Temperature Condition Symbol T Operating Temperature OPER NOTE : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3 required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate ...

  • Page 14

    ... K4T1G044QF K4T1G084QF K4T1G164QF 7.6 Differential input AC logic Level Symbol Parameter V (AC) AC differential input voltage ID V (AC) AC differential cross point voltage IX NOTE : 1. V (AC) specifies the input differential voltage |V ID plementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal The typical value of V (AC) is expected to be about 0 ...

  • Page 15

    ... K4T1G044QF K4T1G084QF K4T1G164QF 9. OCD default characteristics Description Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate NOTE : 1. Absolute Specifications (0°C ≤ T ≤ +95°C; V CASE 2. Impedance measurement condition for output source DC current: V between V and V - 280mV. Impedance measurement condition for output sink dc current: V ...

  • Page 16

    ... K4T1G044QF K4T1G084QF K4T1G164QF 10. IDD Specification Parameters and Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes Symbol Operating one bank active-precharge current; IDD0 tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current ...

  • Page 17

    ... K4T1G044QF K4T1G084QF K4T1G164QF NOTE : 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. ...

  • Page 18

    ... K4T1G044QF K4T1G084QF K4T1G164QF 11. DDR2 SDRAM IDD Spec Table Symbol 800@CL=5 CE7 IDD0 45 IDD1 51 IDD2P 10 IDD2Q 20 IDD2N 25 IDD3P-F 23 IDD3P-S 20 IDD3N 37 IDD4W 67 IDD4R 76 IDD5 105 IDD6 10 IDD7 156 Symbol 800@CL=5 CE7 IDD0 45 IDD1 51 IDD2P 10 IDD2Q 20 IDD2N 25 IDD3P-F 23 IDD3P-S 20 IDD3N 37 IDD4W 72 IDD4R 80 IDD5 105 ...

  • Page 19

    ... K4T1G044QF K4T1G084QF K4T1G164QF Symbol 800@CL=5 CE7 IDD0 55 IDD1 65 IDD2P 10 IDD2Q 22 IDD2N 29 IDD3P-F 25 IDD3P-S 20 IDD3N 40 IDD4W 95 IDD4R 105 IDD5 110 IDD6 10 IDD7 180 datasheet 64Mx16 (K4T1G164QF) 800@CL=6 667@CL=5 CF7 CE6 105 95 110 105 10 10 180 165 - 19 - Rev. 1.11 DDR2 SDRAM Unit NOTE ...

  • Page 20

    ... K4T1G044QF K4T1G084QF K4T1G164QF 12. Input/Output capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS 13. Electrical Characteristics & AC Timing for DDR2-800/667 (0 ° ...

  • Page 21

    ... K4T1G044QF K4T1G084QF K4T1G164QF 13.3 Timing Parameters by Speed Grade (For information related to the entries in this table, refer to both the general notes and the specific notes following this table.) Parameter DQ output access time from CK/CK DQS output access time from CK/CK Average clock HIGH pulse width ...

  • Page 22

    ... K4T1G044QF K4T1G084QF K4T1G164QF Parameter Four Activate Window for 1KB page size products Four Activate Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay ...

  • Page 23

    ... K4T1G044QF K4T1G084QF K4T1G164QF 14. General notes, which may apply for all AC parameters 1. DDR2 SDRAM AC timing reference load Figure 3 represents the timing reference load used in defining the relevant timing parameters of the part not intended to be either a precise repre sentation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other sim- ulation tools to correlate the timing reference load to a system environment ...

  • Page 24

    ... K4T1G044QF K4T1G084QF K4T1G164QF 4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode depen- dent ...

  • Page 25

    ... K4T1G044QF K4T1G084QF K4T1G164QF 15. Specific Notes for dedicated AC parameters 1. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing. ...

  • Page 26

    ... K4T1G044QF K4T1G084QF K4T1G164QF [ Table 3 ] DDR2-400/533 tDS1/tDH1 derating with single-ended data strobe ∆tDS1, ∆tDH1 Derating Values for DDR2-400, DDR2-533(All units in ‘ps’; the note applies to the entire table) 2.0 V/ns 1.5 V/ns ∆tDS ∆tDH ∆tDS ∆tDH 2.0 188 188 167 146 1.5 ...

  • Page 27

    ... K4T1G044QF K4T1G084QF K4T1G164QF DQS DQS V DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Setup Slew Rate Falling Signal Figure 7. IIIustration of nominal slew rate for tDS (differential DQS,DQS) datasheet tDH tDS REF region nominal slew rate tVAC ∆TF ∆TR V (DC (AC)max ...

  • Page 28

    ... K4T1G044QF K4T1G084QF K4T1G164QF V DDQ V (AC)min DQS IH V (DC)min IH Note1 V (DC) REF V (DC)max IL V (AC)max DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Setup Slew Rate Falling Signal NOTE : DQS signal must be monotonic between V Figure 8. IIIustration of nominal slew rate for tDS (single-ended DQS) ...

  • Page 29

    ... K4T1G044QF K4T1G084QF K4T1G164QF DQS DQS V DDQ V (AC)min IH V region V (DC)min IH V (DC) REF V (DC)max IL V (AC)max IL nominal line V SS Setup Slew Rate Falling Signal Figure 9. IIIustration of tangent line for tDS (differential DQS, DQS) datasheet tDH tDS nominal line to ac REF tangent line ∆ ...

  • Page 30

    ... K4T1G044QF K4T1G084QF K4T1G164QF V DDQ V (AC)min DQS IH V (DC)min IH Note1 V (DC) REF V (DC)max IL V (AC)max DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max IL nominal line V SS Setup Slew Rate Falling Signal NOTE : DQS signal must be monotonic between V Figure 10. IIIustration of tangent line for tDS (single-ended DQS) ...

  • Page 31

    ... K4T1G044QF K4T1G084QF K4T1G164QF DQS DQS V DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Hold Slew Rate Rising Signal Figure 11. IIIustration of nominal slew rate for tDH (differential DQS, DQS) datasheet tDS tDH REF region nominal REF slew rate region ∆TR V (DC ...

  • Page 32

    ... K4T1G044QF K4T1G084QF K4T1G164QF V DDQ V (AC)min DQS IH V (DC)min IH Note1 V (DC) REF V (DC)max IL V (AC)max DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Hold Slew Rate Rising Signal NOTE : DQS signal must be monotonic between V Figure 12. IIIustration of nominal slew rate for tDH (single-ended DQS) ...

  • Page 33

    ... K4T1G044QF K4T1G084QF K4T1G164QF DQS DQS V DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Hold Slew Rate tangent line [ V Rising Signal Figure 13. IIIustration of tangent line for tDH (differential DQS, DQS) datasheet tDH tDS REF region tangent line REF region nominal line ∆ ...

  • Page 34

    ... K4T1G044QF K4T1G084QF K4T1G164QF V DDQ V (AC)min DQS IH V (DC)min IH Note1 V (DC) REF V (DC)max IL V (AC)max DDQ V (AC)min IH V (DC)min region V (DC) REF region V (DC)max IL V (AC)max tangent line [ V Hold Slew Rate = Rising Signal NOTE : DQS signal must be monotonic between V Figure 14. IIIustration of tangent line for tDH (single-ended DQS) ...

  • Page 35

    ... K4T1G044QF K4T1G084QF K4T1G164QF 9. tIS and tIH (input setup and hold) derating Derating values for DDR2-400, DDR2-533 [ Table 4 ] 2.0 V/ns ∆tIS 4.0 +187 3.5 +179 3.0 +167 2.5 +150 2.0 +125 1.5 +83 1.0 0 0.9 -11 Command/ 0.8 -25 Address Slew 0.7 -43 rate(V/ns) 0.6 -67 0.5 -110 0 ...

  • Page 36

    ... K4T1G044QF K4T1G084QF K4T1G164QF [ Table 5 ] Derating values for DDR2-667, DDR2-800 2.0 V/ns ∆tIS 4.0 +150 3.5 +143 3.0 +133 2.5 +120 2.0 +100 1.5 +67 1.0 0 0.9 -5 Command/ 0.8 -13 Address Slew 0.7 -22 rate(V/ns) 0.6 -34 0.5 -60 0.4 -100 0.3 -168 0.25 -200 0.2 -325 ...

  • Page 37

    ... K4T1G044QF K4T1G084QF K4T1G164QF DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Setup Slew Rate Falling Signal datasheet tIH tIS REF region nominal slew rate ∆TF ∆TR V (DC (AC)max Setup Slew Rate REF IL = Rising Signal ∆TF Figure 15. IIIustration of nominal slew rate for tIS ...

  • Page 38

    ... K4T1G044QF K4T1G084QF K4T1G164QF DDQ V (AC)min IH V region V (DC)min IH V (DC) REF V (DC)max IL V (AC)max IL nominal line V SS Setup Slew Rate Falling Signal datasheet tIH tIS nominal line to ac REF tangent line ∆TR tangent line[V Setup Slew Rate = Rising Signal ∆TF tangent line[V ...

  • Page 39

    ... K4T1G044QF K4T1G084QF K4T1G164QF DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Hold Slew Rate Rising Signal datasheet tIH tIS REF region nominal REF slew rate region ∆TR (DC (DC)max V REF IL Hold Slew Rate = ∆TR Falling Signal Figure 17. IIIustration of nominal slew rate for tIH ...

  • Page 40

    ... K4T1G044QF K4T1G084QF K4T1G164QF DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Hold Slew Rate Rising Signal datasheet tIH tIS REF region tangent REF line region nominal line ∆TR tangent line [ V (DC (DC)max ] REF IL = ∆TR tangent line [ V Hold Slew Rate = Falling Signal Figure 18 ...

  • Page 41

    ... K4T1G044QF K4T1G084QF K4T1G164QF 10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. MIN ( tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH) ...

  • Page 42

    ... K4T1G044QF K4T1G084QF K4T1G164QF 20. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V differential data strobe crosspoint for a rising signal, and from the input signal crossing at the V a falling signal applied to the device under test. DQS, DQS signals must be monotonic between V 21 ...

  • Page 43

    ... K4T1G044QF K4T1G084QF K4T1G164QF 24. tWTR is at lease two clocks (2 x tCK nCK) independent of operation frequency. 25. Input waveform timing with single-ended data strobe enabled MR[bit10 referenced from the input signal crossing at the V gle-ended data strobe crossing V (DC) at the start of its transition for a rising signal, and from the input signal crossing at the V ...

  • Page 44

    ... K4T1G044QF K4T1G084QF K4T1G164QF Definitions : - tCK(avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window. N ∑ /N tCK(avg) = tCK 200 where - tCH(avg) and tCL(avg) tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses. N ∑ /(N x tCK(avg)) ...

  • Page 45

    ... K4T1G044QF K4T1G084QF K4T1G164QF 36. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and max of SPEC values are to be used for calculations in the table below.) ...

  • Page 46

    ... K4T1G044QF K4T1G084QF K4T1G164QF 44. For tAOFD of DDR2-400/533, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH, input clock HIGH pulse width of 0.5 relative to tCK. tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH offset present at the DRAM input with respect to 0.5. ...