K4T1G164QF-BCE6 Samsung Semiconductor, K4T1G164QF-BCE6 Datasheet - Page 36

• Manufacturer Part Number: K4T1G164QF-BCE6
• Manufacturer: Samsung Semiconductor

Specifications of K4T1G164QF-BCE6

• Lead Free Status / Rohs Status: Compliant

K4T1G044QF
K4T1G084QF
K4T1G164QF
[ Table 5 ] Derating values for DDR2-667, DDR2-800
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the ∆tIS
and ∆tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + ∆tIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V
the actual signal is always earlier than the nominal slew rate line between shaded ’V
Figure 15). If the actual signal is later than the nominal slew rate line anywhere between shaded ’V
the actual signal from the ac level to dc level is used for derating value (see Figure 16).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V
the actual signal is always later than the nominal slewrate line between shaded ’dc to V
ure 17). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to V
the actual signal from the dc level to V
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V
transition) a valid input signal is still required to complete the transition and reach V
For slew rates in between the values listed in Table 4 and Table 5 the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Address Slew
Command/
rate(V/ns)
0.25
0.15
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
-1000
+150
+143
+133
+120
+100
-100
-168
-200
-325
-517
∆tIS
+67
-13
-22
-34
-60
-5
0
REF
2.0 V/ns
(DC) level is used for derating value (see Figure 18).
∆tIS and ∆tIH Derating Values for DDR2-667, DDR2-800
-1125
-125
-188
-292
-375
-500
-708
∆tIH
+94
+89
+83
+75
+45
+21
-14
-31
-54
-83
0
datasheet
+180
+173
+163
+150
+130
-138
-170
-295
-487
-970
∆tIS
+97
+30
+25
+17
-30
-70
+8
-4
1.5 V/ns
CK, CK Differential Slew Rate
- 36 -
-1095
+124
+119
+113
+105
-158
-262
-345
-470
-678
∆tIH
+75
+51
+30
+16
-24
-53
-95
-1
IH/IL
REF
REF
(AC).
(DC) to ac region’, use nominal slew rate for derating value (see
(DC) region’, use nominal slew rate for derating value (see Fig-
+210
+203
+193
+180
+160
+127
-108
-140
-265
-457
-940
∆tIS
+60
+55
+47
+38
+26
-40
REF
0
(DC) to ac region’, the slew rate of a tangent line to
1.0 V/ns
REF
IH
REF
IL
REF
(DC)min and the first crossing of V
(DC) region’, the slew rate of a tangent line to
(DC)max and the first crossing of V
(DC) and the first crossing of V
(DC) and the first crossing of V
-1065
+154
+149
+143
+135
+105
∆tIH
-128
-232
-315
-440
-648
+81
+60
+46
+29
-23
-65
+6
IH/IL
(AC) at the time of the rising clock
DDR2 SDRAM
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
IL
Rev. 1.11
(AC)max. If
REF
NOTE
IH
REF
(AC)min.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(DC). If
(DC).