ADSP-2187LKSTZ-210 Analog Devices Inc, ADSP-2187LKSTZ-210 Datasheet - Page 16

• Manufacturer Part Number: ADSP-2187LKSTZ-210
• Description: IC DSP CONTRLR 16BIT 100-TQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2187LKSTZ-210

• Interface: Host Interface, Serial Port
• Clock Rate: 52MHz
• Non-volatile Memory: External
• On-chip Ram: 160kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 52.5MHz
• Mips: 52.5
• Device Input Clock Speed: 52.5MHz
• Ram Size: 160KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP-2187LKSTZ210

ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed
when the EZ-ICE is not being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals changes. Design the system to be compatible with
the following system interface signal changes introduced by the
EZ-ICE board:
ADDITIONAL INFORMATION
This data sheet provides a general overview of ADSP-218xL
series functionality. For additional information on the architec-
ture and instruction set of the processor, refer to the ADSP-218x
DSP Hardware Reference and the ADSP-218x DSP Instruction
Set Reference.
• EZ-ICE emulation introduces an 8 ns propagation
• EZ-ICE emulation introduces an 8 ns propagation
• EZ-ICE emulation ignores RESET and BR, when
• EZ-ICE emulation ignores RESET and BR when in Emula-
• EZ-ICE emulation ignores the state of target BR in certain
delay between the target circuitry and the DSP on the
RESET signal.
delay between the target circuitry and the DSP on the BR
signal.
single-stepping.
tor Space (DSP halted).
modes. As a result, the target system may take control of
the DSP’s external memory bus only if bus grant (BG) is
asserted by the EZ-ICE board’s DSP.
Rev. C | Page 16 of 48 | January 2008