ADSP-2187LKSTZ-210 Analog Devices Inc, ADSP-2187LKSTZ-210 Datasheet - Page 7

• Manufacturer Part Number: ADSP-2187LKSTZ-210
• Description: IC DSP CONTRLR 16BIT 100-TQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2187LKSTZ-210

• Interface: Host Interface, Serial Port
• Clock Rate: 52MHz
• Non-volatile Memory: External
• On-chip Ram: 160kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 52.5MHz
• Mips: 52.5
• Device Input Clock Speed: 52.5MHz
• Ram Size: 160KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP-2187LKSTZ210

faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 2
ADSP-218xL series, two serial devices, a byte-wide EPROM,
and optional external program and data overlay memories
(mode-selectable). Programmable wait state generation allows
the processor to connect easily to slow peripheral devices.
ADSP-218xL series members also provide four external inter-
rupts and two serial ports or six external interrupts and one
serial port. Host Memory Mode allows access to the full external
data bus, but limits addressing to a single address bit (A0).
Through the use of external hardware, additional system
peripherals can be added in this mode to generate and latch
address signals.
Clock Signals
ADSP-218xL series members can be clocked by either a crystal
or a TTL-compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
nor operated below the specified frequency during normal oper-
ation. The only exception is while the processor is in the
shows typical basic system configurations with the
1/2
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
OR
CLOCK
FULL MEMORY MODE
MODE C/PF2
MODE A/PF0
MODE B/PF1
CLKIN
XTAL
MODE D/PF3
SCLK1
RFS1 OR IRQ0
TFS1 OR
DT1 OR FO
DR1 OR FI
FL0–2
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
SCLK0
RFS0
TFS0
DT0
DR0
SPORT0
SPORT1
ADSP-218xL
IRQ1
ADDR13–0
DATA23–0
PW DACK
IOMS
PWD
BGH
BMS
PMS
DMS
CMS
WR
BR
BG
RD
14
24
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Rev. C | Page 7 of 48 | January 2008
A13–0
D23–16
D15–8
A10–0
D23–8
A13–0
D23–0
Figure 2. Basic System Interface
A0–A21
DATA
CS
ADDR
DATA
CS
ADDR
DATA
DM SEGMEN TS
2048 LOCATIONS
PM SEGMEN TS
(PERIPHERALS)
NOTE: MODE D APPLIES TO THE ADSP-2187L P ROCES SOR ON LY
MEMORY
OVERLAY
MEMORY
TWO 8K
I/O SPACE
TWO 8K
BYTE
power-down state. For additional information, refer to the
ADSP-218x DSP Hardware Reference, for detailed information
on this power-down feature.
If an external clock is used, it should be a TTL-compatible signal
running at half the instruction rate. The signal is connected to
the processor’s CLKIN input. When an external clock is used,
the XTAL pin must be left unconnected.
ADSP-218xL series members use an input clock with a fre-
quency equal to half the instruction rate; a 40 MHz input clock
yields a 12.5 ns processor cycle (which is equivalent to
80 MHz). Normally, instructions are executed in a single pro-
cessor cycle. All device timing is relative to the internal
instruction clock rate, which is indicated by the CLKOUT signal
when enabled.
Because ADSP-218xL series members include an on-chip oscil-
lator circuit, an external crystal may be used. The crystal should
be connected across the CLKIN and XTAL pins, with two
capacitors connected as shown in
dependent on crystal type and should be specified by the crystal
manufacturer. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used. To provide an
adequate feedback path around the internal amplifier circuit,
place a resistor in parallel with the circuit, as shown in
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled by
the CLKODIS bit in the SPORT0 Autobuffer Control Register.
µCONTROLLER
INTERFACE
1/2
SYSTEM
CRYSTAL
OR
OR
DEVICE
SERIAL
SERIAL
DEVICE
CLOCK
16
HOST MEMORY MODE
CLK IN
IRQ2/PF7
IRQL1/PF6
MODE D/PF3
MODE C/PF2
MODE A/PF0
MODE B/PF1
XTAL
FL0–2
IRQE/PF4
IRQL0/PF5
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SCLK0
RFS0
TFS0
DT0
DR0
IRD/D6
IWR/D7
IACK/D3
IDMA PORT
IS/D4
IAL/D5
IAD15-0
SPORT0
SPORT1
ADSP-218xL
Figure
DATA23–8
PW DACK
IOMS
3. Capacitor values are
BMS
DMS
CMS
BGH
PWD
PMS
WR
RD
BR
BG
A0
1
16
Figure
3.