ADSP-2187LKSTZ-210 Analog Devices Inc, ADSP-2187LKSTZ-210 Datasheet - Page 28

• Manufacturer Part Number: ADSP-2187LKSTZ-210
• Description: IC DSP CONTRLR 16BIT 100-TQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2187LKSTZ-210

• Interface: Host Interface, Serial Port
• Clock Rate: 52MHz
• Non-volatile Memory: External
• On-chip Ram: 160kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 52.5MHz
• Mips: 52.5
• Device Input Clock Speed: 52.5MHz
• Ram Size: 160KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP-2187LKSTZ210

ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Serial Ports
Table 19. Serial Ports
1
2
3
Parameter
Timing Requirements:
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
For the ADSP-2187L, this specification is 38 ns min.
For the ADSP-2187L, this specification is 7 ns min.
For the ADSP-2185L, and the ADSP-2187L, this specification is 15 ns min.
SCK
SCS
SCH
SCP
CC
SCDE
SCDV
RH
RD
SCDH
TDE
TDV
SCDD
RDV
SCLK Period
DR/TFS/RFS Setup Before SCLK Low
DR/TFS/RFS Hold After SCLK Low
SCLKIN Width
CLKOUT High to SCLKOUT
SCLK High to DT Enable
SCLK High to DT Valid
TFS/RFS
TFS/RFS
DT Hold after SCLK High
TFS (Alt) to DT Enable
TFS (Alt) to DT Valid
SCLK High to DT Disable
RFS (Multichannel, Frame Delay Zero) to DT Valid
OUT
OUT
Hold After SCLK High
Delay from SCLK High
1
3
2
Rev. C | Page 28 of 48 | January 2008
Min
50
4
8
20
0.25t
0
0
0
0
CK
Max
0.25t
15
15
14
15
15
CK
+ 10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns