ADSP-2187LKSTZ-210 Analog Devices Inc, ADSP-2187LKSTZ-210 Datasheet - Page 17

• Manufacturer Part Number: ADSP-2187LKSTZ-210
• Description: IC DSP CONTRLR 16BIT 100-TQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2187LKSTZ-210

• Interface: Host Interface, Serial Port
• Clock Rate: 52MHz
• Non-volatile Memory: External
• On-chip Ram: 160kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 52.5MHz
• Mips: 52.5
• Device Input Clock Speed: 52.5MHz
• Ram Size: 160KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP-2187LKSTZ210

PIN DESCRIPTIONS
ADSP-218xL series members are available in a 100-lead LQFP
package and a 144-ball BGA package. In order to maintain max-
imum functionality and reduce package size and pin count,
some serial port, programmable flag, interrupt and external bus
pins have dual, multiplexed functionality. The external bus pins
are configured during RESET only, while serial port pins are
Table 9. Common-Mode Pins
Pin Name
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2/
PF7
IRQL1/
PF6
IRQL0/
PF5
IRQE/
PF4
Mode D
PF3
Mode C/
PF2
Mode B/
PF1
Mode A/
PF0
CLKIN
XTAL
CLKOUT
SPORT0
SPORT1/
IRQ1–0, FI, FO
PWD
PWDACK
FL0, FL1, FL2
V
V
GND
DDINT
DDEXT
2
/
No. of Pins
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
5
1
1
3
2
4
10
I/O
I
I
O
O
O
O
O
O
O
O
O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
O
O
I/O
I/O
I
O
O
I
I
I
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Rev. C | Page 17 of 48 | January 2008
Function
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive Interrupt Request
Programmable I/O Pin
Level-Sensitive Interrupt Requests
Programmable I/O Pin
Level-Sensitive Interrupt Requests
Programmable I/O Pin
Edge-Sensitive Interrupt Requests
Programmable I/O Pin
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Mode Select Input—Checked Only During RESET
Programmable I/O Pin During Normal Operation
Clock Input
Quartz Crystal Output
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts, FI, FO
Power-Down Control Input
Power-Down Acknowledge Control Output
Output Flags
Internal V
External V
Ground (LQFP)
DD
DD
(1.8 V) Power (LQFP)
software configurable during program execution. Flag and
interrupt functionality is retained concurrently on multiplexed
pins. In cases where pin functionality is reconfigurable, the
default state is shown in plain text in
functionality is shown in italics.
(1.8 V, 2.5 V, or 3.3 V) Power (LQFP)
1
1
1
3
1
Table
9, while alternate