IC SPARTAN-3AN FPGA 200K 256FTBG

XC3S200AN-4FTG256C

Manufacturer Part NumberXC3S200AN-4FTG256C
DescriptionIC SPARTAN-3AN FPGA 200K 256FTBG
ManufacturerXilinx Inc
SeriesSpartan™-3AN
XC3S200AN-4FTG256C datasheets
Product Change Notification
 

Specifications of XC3S200AN-4FTG256C

Total Ram Bits294912Number Of Logic Elements/cells4032
Number Of Labs/clbs448Number Of I /o195
Number Of Gates200000Voltage - Supply1.14 V ~ 1.26 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case256-LBGANo. Of Logic Blocks4032
No. Of Gates200000No. Of Macrocells4032
Family TypeSpartan-3ANNo. Of Speed Grades4
No. Of I/o's195Package256FTBGA
Family NameSpartan®-3ANDevice Logic Units4032
Device System Gates200000Maximum Internal Frequency667 MHz
Typical Operating Supply Voltage1.2 VMaximum Number Of User I/os195
Ram Bits294912Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other names122-1553  
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DS557 April 1, 2011
Module 1:
Introduction and Ordering Information
DS557 (v4.1) April 1, 2011
Introduction
Features
Architectural Overview
Configuration Overview
In-system Flash Memory Overview
General I/O Capabilities
Supported Packages and Package Marking
Ordering Information
Module 2:
Functional Description
DS557 (v4.1) April 1, 2011
The functionality of the Spartan®-3AN FPGA family is
described in the following documents:
UG331: Spartan-3 Generation FPGA User Guide
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
-
Distributed RAM
-
SRL16 Shift Registers
-
Carry and Arithmetic Logic
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE® Design Tools and IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Power Management
UG332: Spartan-3 Generation Configuration User Guide
Configuration Overview
Configuration Pins and Behavior
Bitstream Sizes
Detailed Descriptions by Mode
-
Self-contained In-System Flash mode
-
Master Serial Mode using Platform Flash PROM
-
Master SPI Mode using Commodity Serial Flash
-
Master BPI Mode using Commodity Parallel Flash
-
Slave Parallel (SelectMAP) using a Processor
-
Slave Serial using a Processor
-
JTAG Mode
ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Design Authentication using Device DNA
UG333: Spartan-3AN In-System Flash User Guide
UG334: Spartan-3AN Starter Kit User Guide
© Copyright 2007–2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS557 April 1, 2011
Product Specification
1
Spartan-3AN FPGA Family Data Sheet
Module 3:
DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
DC Electrical Characteristics
Switching Characteristics
Module 4:
Pinout Descriptions
DS557 (v4.1) April 1, 2011
Pin Descriptions
Package Overview
Pinout Tables
Footprint Diagrams
Table 1: Production Status of Spartan-3AN FPGAs
Spartan-3AN FPGA
Additional information on the Spartan-3AN family can be
found at http://www.xilinx.com/products/spartan3a/3an.htm.
www.xilinx.com
Product Specification
Absolute Maximum Ratings
Supply Voltage Specifications
Recommended Operating Conditions
I/O Timing
Configurable Logic Block (CLB) Timing
Multiplier Timing
Block RAM Timing
Digital Clock Manager (DCM) Timing
Suspend Mode Timing
Device DNA Timing
Configuration and JTAG Timing
Status
XC3S50AN
Production
XC3S200AN
Production
XC3S400AN
Production
XC3S700AN
Production
XC3S1400AN
Production
1

XC3S200AN-4FTG256C Summary of contents

  • Page 1

    ... Recommended Operating Conditions I/O Timing Configurable Logic Block (CLB) Timing Multiplier Timing Block RAM Timing Digital Clock Manager (DCM) Timing Suspend Mode Timing Device DNA Timing Configuration and JTAG Timing Status XC3S50AN Production XC3S200AN Production XC3S400AN Production XC3S700AN Production XC3S1400AN Production 1 ...

  • Page 2

    ... Scratchpad memory • Robust 100K Flash memory program/erase cycles Table 2: Summary of Spartan-3AN FPGA Attributes Equivalent System Logic Device Gates Cells CLBs XC3S50AN 50K 1,584 176 XC3S200AN 200K 4,032 448 XC3S400AN 400K 8,064 896 XC3S700AN 700K 13,248 1,472 XC3S1400AN 1400K 25,344 2,816 Notes: 1 ...

  • Page 3

    Architectural Overview The Spartan-3AN FPGA architecture is compatible with that of the Spartan-3A FPGA. The architecture consists of five fundamental programmable functional elements: • Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used ...

  • Page 4

    ... MultiBoot FPGA configuration bitstreams or nonvolatile data required by the FPGA application, such as code-shadowed MicroBlaze processor applications. Table 3: Spartan-3AN Device In-System Flash Memory (Figure 2) Part Number XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN Notes: 1. Aligned to next available page location. After configuration, the FPGA design has full access to the in-system Flash memory via an internal SPI interface ...

  • Page 5

    ... Table 4: Available User I/Os and Differential (Diff) I/O Pairs TQ144 (1) Package TQG144 Body Size (mm (3) Device User (4) 108 XC3S50AN (7) XC3S200AN – XC3S400AN – XC3S700AN – XC3S1400AN – Notes: 1. See Pb and Pb-Free Packaging, page 7 2. The footprint for the TQ(G)144 ( mm) package is larger than the package body. ...

  • Page 6

    ... R SPARTAN R TM XC3S50AN Package TQG144 AGQ0725 D1234567A 4C Pin P1 R SPARTAN R TM XC3S200AN FTG256 AGQ0725 Package D1234567A 4C www.xilinx.com Mask Revision Code Fabrication Code Process Technology Date Code Lot Code DS557-1_02_080107 Mask Revision Code Fabrication Code Process Code ...

  • Page 7

    ... The ordering code for the leaded devices does not have an extra ‘G’. Leaded and Pb-free devices have the same pin-out. Table 5: Pb and Pb-Free Package Options Pins Type Material Pb-Free Device Speed Range TQG144 ✔ XC3S50AN - ✔ XC3S200AN - XC3S400AN - XC3S700AN - XC3S1400AN ...

  • Page 8

    ... Ordering Information X-Ref Target - Figure 5 Example: Device Type Speed Grade Package Type/Number of Pins Device Speed Grade XC3S50AN -4 Standard Performance TQ144/ (1) XC3S200AN -5 High Performance XC3S400AN XC3S700AN XC3S1400AN Notes: 1. The -5 speed grade is exclusively available in the Commercial temperature range. 2. See Table 4 and Table 5 for available package combinations. ...

  • Page 9

    Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY ...

  • Page 10

    DS557 (v4.1) April 1, 2011 Spartan-3AN FPGA Design Documentation The functionality of the Spartan®-3AN FPGA family is described in the following documents. The topics covered in each guide are listed below: • DS706: Extended Spartan-3A Family Overview • UG331: Spartan-3 ...

  • Page 11

    Related Product Families The Spartan-3AN FPGA family is generally compatible with the Spartan-3A FPGA family. • DS529: Spartan-3A FPGA Family Data Sheet Revision History The following table shows the revision history for this document. Date Version 02/26/07 1.0 Initial release. ...

  • Page 12

    DS557 (v4.1) April 1, 2011 DC Electrical Characteristics In this section, specifications can be designated as Advance, Preliminary, or Production. These terms are defined as follows: Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristics ...

  • Page 13

    Power Supply Specifications Table 7: Supply Voltage Thresholds for Power-On Reset Symbol V Threshold for the V CCINTT V Threshold for the V CCAUXT V Threshold for the V CCO2T Notes: 1. When configuring from the In-System Flash, V reaches ...

  • Page 14

    General Recommended Operating Conditions Table 10: General Recommended Operating Conditions Symbol T Junction temperature J V Internal supply voltage CCINT (1) V Output driver supply voltage CCO V Auxiliary supply voltage CCAUX (2) V Input voltage IN T Input signal ...

  • Page 15

    General DC Characteristics for I/O Pins Table 11: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol Description (2) I Leakage current at User I/O, L Input-only, Dual-Purpose, and Dedicated pins, FPGA powered I Leakage current on pins ...

  • Page 16

    ... XC3S700AN XC3S1400AN XC3S50AN 0.2 XC3S200AN 0.2 XC3S400AN 0.3 XC3S700AN 0.3 XC3S1400AN 0.3 XC3S50AN 3.1 XC3S200AN 5.1 XC3S400AN 5.1 XC3S700AN 6.1 XC3S1400AN 10.1 Table 10. of 25° 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, a design with no CCAUX provides quick, approximate, typical estimates, and does not require a netlist of the design, and b) www ...

  • Page 17

    Single-Ended I/O Standards Table 13: Recommended Operating Conditions for User I/Os Using Single-Ended Standards V IOSTANDARD CCO Attribute Min (V) Nom (V) LVTTL 3.0 (4) LVCMOS33 3.0 (4)(5) LVCMOS25 2.3 LVCMOS18 1.65 LVCMOS15 1.4 LVCMOS12 1.1 (6) PCI33_3 3.0 (6) ...

  • Page 18

    Table 14: DC Characteristics of User I/Os Using Single-Ended Standards Test Conditions IOSTANDARD Attribute (mA) (mA) (3) LVTTL 2 2 – – – – – –16 ...

  • Page 19

    Differential I/O Standards Differential Input Pairs X-Ref Target - Figure 6 Internal Logic V INN V INP GND level Table 15: Recommended Operating Conditions for User I/Os Using Differential Signal Standards V CCO IOSTANDARD Attribute Min (V) (3) LVDS_25 2.25 ...

  • Page 20

    Table 15: Recommended Operating Conditions for User I/Os Using Differential Signal Standards (Cont’d) V CCO IOSTANDARD Attribute Min (V) (8) DIFF_SSTL3_II 3.0 Notes: 1. The V rails supply only differential output drivers, not input circuits. CCO 2. V must be ...

  • Page 21

    Table 16: DC Characteristics of User I/Os Using Differential Signal Standards IOSTANDARD Attribute Min (mV) LVDS_25 247 LVDS_33 247 BLVDS_25 240 MINI_LVDS_25 300 MINI_LVDS_33 300 RSDS_25 100 RSDS_33 100 TMDS_33 400 PPDS_25 100 PPDS_33 100 DIFF_HSTL_I_18 – DIFF_HSTL_II_18 – DIFF_HSTL_III_18 ...

  • Page 22

    External Termination Requirements for Differential I/O LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards X-Ref Target - Figure 3. 2.5V CCO CCO LVDS_33, LVDS_25, MINI_LVDS_33, MINI_LVDS_25, RSDS_33, RSDS_25, PPDS_33 PPDS_25 a) Input-only Differential Pairs or Pairs ...

  • Page 23

    Device DNA Read Endurance Table 17: Device DNA Identifier Memory Characteristics Symbol Number of READ operations or JTAG ISC_DNA read operations. Unaffected by DNA_CYCLES HOLD or SHIFT operations In-System Flash Memory Data Retention, Program/Write Endurance Table 18: In-System Flash (ISF) ...

  • Page 24

    ... Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to the simulation netlist. Table 19: Spartan-3AN Family v1.41 Speed Grade Designations Device XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN Table 20 provides the recent history of the Spartan-3AN speed files. ...

  • Page 25

    ... XC3S50AN output drive, Fast slew XC3S200AN (3) rate, with DCM XC3S400AN XC3S700AN XC3S1400AN (2) LVCMOS25 , 12 mA XC3S50AN output drive, Fast slew XC3S200AN rate, without DCM XC3S400AN XC3S700AN XC3S1400AN Table 30 and are based on the operating conditions set forth in www.xilinx.com Speed Grade -5 -4 Units Max Max 3 ...

  • Page 26

    ... DCM XC3S400AN XC3S700AN XC3S1400AN (3) LVCMOS25 , XC3S50AN IFD_DELAY_VALUE = 5, XC3S200AN without DCM XC3S400AN XC3S700AN XC3S1400AN Table 30 and are based on the operating conditions set forth in Table 26. If this is true of the data Input, add the Table 26. If this is true of the data Input, subtract the www ...

  • Page 27

    ... The Input Delay is programmed. DS557 (v4.1) April 1, 2011 Product Specification Spartan-3AN FPGA Family: DC and Switching Characteristics IFD_ Conditions DELAY_ Device VALUE (2) LVCMOS25 0 XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN (2) LVCMOS25 1 XC3S50AN XC3S200AN XC3S400AN www.xilinx.com Speed Grade -5 -4 Units Min Min 1.56 1.58 ns 1.71 1. ...

  • Page 28

    ... DELAY_ Device VALUE (2) LVCMOS25 1 XC3S700AN XC3S1400AN (3) LVCMOS25 XC3S50AN XC3S200AN 0 XC3S400AN XC3S700AN XC3S1400AN (3) LVCMOS25 1 XC3S50AN XC3S200AN www.xilinx.com Speed Grade -5 -4 Units Min Min 1.82 1.95 ns 2.62 2.83 ns 3.32 3.72 ns 3.83 4.31 ns 3.69 4.14 ns 4.60 5.19 ns 5.39 6.10 ns 5.92 6.73 ns 1.79 2.17 ns 2.55 2 ...

  • Page 29

    Table 23: Setup and Hold Times for the IOB Input Path (Cont’d) Symbol Description T Time from the active transition at the IOICKPD ICLK input of the Input Flip-Flop (IFF) to the point where data must be held at the ...

  • Page 30

    ... XC3S200AN 1.57 1.65 ns 1.87 1.97 ns 2.16 2.33 ns 2.68 2.96 ns 2.87 3.19 ns 3.20 3.60 ns 3.57 4.02 ns 3.79 4.26 ns 3.42 3.86 ns 3.79 4. ...

  • Page 31

    ... Speed Grade Device Units -5 -4 Max Max XC3S200AN 5.43 6.24 ns 5.75 6.59 ns XC3S400AN 1.32 1.43 ns 1.67 1.83 ns 1.90 2.07 ns 2.33 2.52 ns 2.60 2.91 ns 2.94 3.20 ns 3.23 3.51 ns 3.50 3.85 ns 3.18 3.55 ns 3.53 3.95 ns 3.76 4.20 ns 4.26 4.67 ns 4.51 4.97 ns 4.85 5 ...

  • Page 32

    ... Max Max XC3S1400AN 3.17 3.52 ns 3.52 3.92 ns 3.82 4.18 ns 4.10 4.57 ns 3.84 4.31 ns 4.20 4.79 ns 4.46 5.06 ns 4.87 5.51 ns 5.07 5.73 ns 5.43 6.08 ns 5.73 6.33 ns 6.01 6.77 ns XC3S50AN 1.70 1.81 ns XC3S200AN 1.85 2.04 ns XC3S400AN 1.44 1.74 ns XC3S700AN 1.48 1.74 ns XC3S1400AN 1.50 1. ...

  • Page 33

    ... Max Max XC3S50AN 2.30 2.41 ns 3.24 3.35 ns 3.65 3.98 ns 4.18 4.55 ns 4.02 4.47 ns 4.86 5.32 ns 5.61 6.17 ns 6.11 6.75 ns XC3S200AN 2.19 2.43 ns 2.86 3.16 ns 3.52 4.01 ns 4.02 4.60 ns 3.83 4.43 ns 4.70 5.46 ns 5.48 6.33 ns 5.99 6.94 ns XC3S400AN 1.93 2.25 ns 2.57 2 ...

  • Page 34

    Table 25: Propagation Times for the IOB Input Path (Cont’d) Symbol Description T The time it takes for data to travel IOPLID from the Input pin through the IFF latch to the I output with the input delay programmed Notes: ...

  • Page 35

    Input Timing Adjustments Table 26: Input Timing Adjustments by IOSTANDARD Convert Input Time from Adjustment Below LVCMOS25 to the Following Signal Standard Speed Grade (IOSTANDARD) -5 Single-Ended Standards LVTTL 0.62 LVCMOS33 0.54 LVCMOS25 0 LVCMOS18 0.83 LVCMOS15 0.60 LVCMOS12 0.31 ...

  • Page 36

    Output Propagation Times Table 27: Timing for the IOB Output Path Symbol Description Clock-to-Output Times T When reading from the Output IOCKP Flip-Flop (OFF), the time from the active transition at the OCLK input to data appearing at the Output ...

  • Page 37

    Three-State Output Propagation Times Table 28: Timing for the IOB Three-State Path Symbol Description Synchronous Output Enable/Disable Times T Time from the active transition at the OTCLK IOCKHZ input of the Three-state Flip-Flop (TFF) to when the Output pin enters ...

  • Page 38

    Output Timing Adjustments Table 29: Output Timing Adjustments for IOB Convert Output Time from Adjustment Below LVCMOS25 with 12 mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL Slow ...

  • Page 39

    Table 29: Output Timing Adjustments for IOB Convert Output Time from Adjustment Below LVCMOS25 with 12 mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) LVCMOS25 Slow 2.82 8 ...

  • Page 40

    Table 29: Output Timing Adjustments for IOB Convert Output Time from Adjustment Below LVCMOS25 with 12 mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) LVCMOS12 Slow 5.67 Fast ...

  • Page 41

    Timing Measurement Methodology When measuring timing parameters at the programmable I/Os, different signal standards call for different test conditions. Table 30 lists the conditions to use for each standard. The method for measuring Input timing is as follows: A signal ...

  • Page 42

    Table 30: Test Methods for Timing Measurement at I/Os (Cont’d) Signal Standard (IOSTANDARD) V REF Differential LVDS_25 – LVDS_33 – BLVDS_25 – MINI_LVDS_25 – MINI_LVDS_33 – LVPECL_25 – LVPECL_33 – RSDS_25 – RSDS_33 – TMDS_33 – PPDS_25 – PPDS_33 – ...

  • Page 43

    ... Ball grid array packages are recommended for applications with a large number of simultaneously switching outputs. Table 31: Equivalent V Device XC3S50AN XC3S200AN XC3S400AN XC3S700AN XC3S1400AN CCO www.xilinx.com and Table 32 provide the essential SSO /GND pairs ...

  • Page 44

    Table 32: Recommended Number of Simultaneously Switching Outputs per V -GND Pair CCO TQG144 Signal Standard (IOSTANDARD) Top, Bottom Banks 0,2 Banks 1,3 Single-Ended Standards LVTTL Slow ...

  • Page 45

    Table 32: Recommended Number of Simultaneously Switching Outputs per V -GND Pair (Cont’d) CCO TQG144 Signal Standard (IOSTANDARD) Top, Bottom Banks 0,2 Banks 1,3 LVCMOS25 Slow – 24 – ...

  • Page 46

    Table 32: Recommended Number of Simultaneously Switching Outputs per V -GND Pair (Cont’d) CCO TQG144 Signal Standard (IOSTANDARD) Top, Bottom Banks 0,2 Banks 1,3 LVCMOS12 Slow – 6 – Fast – 6 – QuietIO ...

  • Page 47

    Configurable Logic Block (CLB) Timing Table 33: CLB (SLICEM) Timing Symbol Clock-to-Output Times T When reading from the FFX (FFY) Flip-Flop, the time CKO from the active transition at the CLK input to data appearing at the XQ (YQ) output ...

  • Page 48

    Table 34: CLB Distributed RAM Switching Characteristics Symbol Clock-to-Output Times T Time from the active edge at the CLK input to data appearing on SHCKO the distributed RAM output Setup Times T Setup time of data at the BX or ...

  • Page 49

    Clock Buffer/Multiplexer Switching Characteristics Table 36: Clock Distribution Switching Characteristics Description Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same as BUFGCE enable CE-input Frequency ...

  • Page 50

    Embedded Multiplier Timing Table 37 Embedded Multiplier Timing Symbol Combinatorial Delay T Combinational multiplier propagation delay from the A and B inputs MULT to the P outputs, assuming 18-bit inputs and a 36-bit product ...

  • Page 51

    Block RAM Timing Table 38: Block RAM Timing Symbol Clock-to-Output Times T When reading from block RAM, the delay from the active RCKO transition at the CLK input to data appearing at the DOUT output Setup Times T Setup time ...

  • Page 52

    Digital Clock Manager (DCM) Timing For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS). Aspects of DLL operation play a role in all DCM applications. ...

  • Page 53

    Table 40: Switching Characteristics for the DLL Symbol Output Frequency Ranges CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs CLKOUT_FREQ_2X Frequency for the CLK2X and CLK2X180 outputs CLKOUT_FREQ_DV Frequency for the CLKDV ...

  • Page 54

    Table 40: Switching Characteristics for the DLL (Cont’d) Symbol Delay Lines (5) DCM_DELAY_STEP Finest delay resolution, average over all taps Notes: 1. The numbers in this table are based on the operating conditions set forth in 2. Indicates the maximum ...

  • Page 55

    Table 42: Switching Characteristics for the DFS Symbol Output Frequency Ranges CLKOUT_FREQ_FX Frequency for the CLKFX and CLKFX180 outputs (2)(3) Output Clock Jitter CLKOUT_PER_JITT_FX Period jitter at the CLKFX and CLKFX180 outputs. (4)(5) Duty Cycle CLKOUT_DUTY_CYCLE_FX Duty cycle precision for ...

  • Page 56

    Phase Shifter (PS) Table 43: Recommended Operating Conditions for the PS in Variable Phase Mode Symbol Operating Frequency Ranges PSCLK_FREQ (F ) Frequency for the PSCLK input PSCLK Input Pulse Requirements PSCLK_PULSE PSCLK pulse width as a percentage of the ...

  • Page 57

    DNA Port Timing Table 46: DNA_PORT Interface Timing Symbol T Setup time on SHIFT before the rising edge of CLK DNASSU T Hold time on SHIFT after the rising edge of CLK DNASH T Setup time on DIN before the ...

  • Page 58

    ... XC3S50AN 2 4 XC3S200AN XC3S400AN XC3S700AN 3 6 XC3S1400AN XC3S50AN 13 32 XC3S200AN XC3S400AN XC3S700AN 15 35 XC3S1400AN XC3S50AN 14 35 XC3S200AN XC3S400AN XC3S700AN XC3S1400AN 17 40 XC3S50AN 15 35 XC3S200AN 30 75 XC3S400AN XC3S700AN 45 100 XC3S1400AN XC3S50AN 0.8 2.5 XC3S200AN 1.6 5 XC3S400AN XC3S700AN XC3S1400AN Units µs µ ...

  • Page 59

    Suspend Mode Timing X-Ref Target - Figure 12 Entering Suspend Mode SUSPEND Input AWAKE Output Flip-Flops, Block RAM, Distributed RAM FPGA Outputs FPGA Inputs, Interconnect Table 49: Suspend Mode Timing Parameters Symbol Entering Suspend Mode T Rising edge of SUSPEND ...

  • Page 60

    ... Spartan-3 Generation Configuration User Guide. www.xilinx.com 1.2V 3.3V 2.5V or 3.3V T ICCK DS557-3_01_052908 , V , and CCINT CCAUX All Speed Grades Device Min Max All – 18 All 0.5 – XC3S50AN – 0.5 XC3S200AN – 0.5 XC3S400AN – 1 XC3S700AN – 2 XC3S1400AN – 2 All 250 – All 0.5 4 Units ms µ µ ...

  • Page 61

    Configuration Clock (CCLK) Characteristics Table 51: Master Mode CCLK Output Period by ConfigRate Option Setting Symbol Description CCLK clock period by T ConfigRate setting CCLK1 T CCLK3 T CCLK6 T CCLK7 T CCLK8 T CCLK10 T CCLK12 T CCLK13 T ...

  • Page 62

    Table 52: Master Mode CCLK Output Frequency by ConfigRate Option Setting Symbol Description Equivalent CCLK clock frequency F by ConfigRate setting CCLK1 F CCLK3 F CCLK6 F CCLK7 F CCLK8 F CCLK10 F CCLK12 F CCLK13 F CCLK17 F CCLK22 ...

  • Page 63

    Table 54: Slave Mode CCLK Input Low and High Time Symbol T CCLK Low and High time SCCL, T SCCH Master Serial and Slave Serial Mode Timing X-Ref Target - Figure 14 PROG_B (Input) INIT_B (Open-Drain) CCLK (Input/Output) DIN (Input) ...

  • Page 64

    Slave Parallel Mode Timing X-Ref Target - Figure 15 PROG_B (Input) INIT_B (Open-Drain) CSI_B (Input) RDWR_B (Input) CCLK (Input (Inputs) Notes possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, ...

  • Page 65

    External Serial Peripheral Interface (SPI) Configuration Timing X-Ref Target - Figure 16 PROG_B (Input) PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process. (Input) VS[2:0] <1:1:1> (Input) M[2:0] <0:0:1> (Input) T MINIT INIT_B (Open-Drain) ...

  • Page 66

    Table 58: Configuration Timing Requirements for Attached SPI Serial Flash Symbol T SPI serial Flash PROM chip-select time CCS T SPI serial Flash PROM data input setup time DSU T SPI serial Flash PROM data input hold time DH T ...

  • Page 67

    Table 59: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode Symbol T Initial CCLK clock period CCLK1 T CCLK clock period after FPGA loads ConfigRate setting CCLKn T Setup time on M[2:0] mode pins before the rising edge of INIT_B ...

  • Page 68

    ... All functions except those shown below Configuration commands (CFG_IN, ISC_PROGRAM) All functions except ISC_DNA command During ISC_DNA command All operations on XC3S50AN, XC3S200AN, and XC3S400AN FPGAs and for BYPASS or HIGHZ instructions on all FPGAs All operations on XC3S700AN and XC3S1400AN FPGAs, except for BYPASS or HIGHZ instructions Table www ...

  • Page 69

    ... Date Version 02/26/07 1.0 Initial release. 08/16/07 2.0 Updated for Production release of initial device (XC3S200AN). Timing specifications updated for v1.38 speed files. DC specifications updated with production values. Other changes throughout. 08/31/07 2.0.1 Updated for Production release of XC3S1400AN. Improved t 09/12/07 2.0.2 Updated for Production release of XC3S700AN. ...

  • Page 70

    Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY ...

  • Page 71

    DS557 (v4.1) April 1, 2011 Introduction This section describes how the various pins on a Spartan®-3AN FPGA connect within the supported component packages, and provides device-specific thermal characteristics. For general information on the pin functions and the package characteristics, see ...

  • Page 72

    Table 62: Types of Pins on Spartan-3AN FPGAs (Cont’d) Type with Color Code Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every package has two dedicated configuration pins. These pins are powered by VCCAUX. See UG332: ...

  • Page 73

    ... Table 64: Maximum User I/O by Package Maximum User I/Os Device Package and Input-Only TQG144 108 XC3S50AN FTG256 144 XC3S200AN FTG256 195 FTG256 195 XC3S400AN FGG400 311 XC3S700AN FGG484 372 FGG484 375 XC3S1400AN FGG676 502 Notes: 1. Some VREFs are on INPUT pins. See pinout tables for details. ...

  • Page 74

    ... The “Still Air (0 LFM)” column shows the  a fan. The thermal resistance drops with increasing air flow. Table 67: Spartan-3AN FPGA Package Thermal Characteristics Junction-to-Case (1) Device Package TQG144 XC3S50AN FTG256 XC3S200AN FTG256 FTG256 XC3S400AN FGG400 XC3S700AN FGG484 FGG484 XC3S1400AN FGG676 Notes: 1 ...

  • Page 75

    TQG144: 144-lead Thin Quad Flat Package The XC3S50AN is available in the 144-lead thin quad flat package, TQG144. Table 68 lists all the package pins. They are sorted by bank number and then by pin name. Pins that form a ...

  • Page 76

    Table 68: Spartan-3AN TQG144 Pinout (Cont’d) Bank Pin Name 2 IO_L05P_2 2 IO_L06N_2/D6 2 IO_L06P_2 2 IO_L07N_2/D4 2 IO_L07P_2/D5 2 IO_L08N_2/GCLK15 2 IO_L08P_2/GCLK14 2 IO_L09N_2/GCLK1 2 IO_L09P_2/GCLK0 2 IO_L10N_2/GCLK3 2 IO_L10P_2/GCLK2 2 IO_L11N_2/DOUT 2 IO_L11P_2/AWAKE 2 IO_L12N_2/D3 2 IO_L12P_2/INIT_B 2 ...

  • Page 77

    User I/Os by Bank Table 69 indicates how the 108 available user-I/O pins are distributed between the four I/O banks on the TQG144 package. The AWAKE pin is counted as a dual-purpose I/O. Table 69: User I/Os Per Bank for ...

  • Page 78

    TQG144 Footprint Note: Pin 1 indicator in top-left corner and logo orientation. X-Ref Target - Figure 19 TMS 1 TDI 2 X IO_L02P_3 3 IO_L01P_3 4 IO_L02N_3 5 IO_L01N_3 6 IO_L03P_3 7 IO_L03N_3 8 GND 9 IO_L04P_3 10 IO_L04N_3/VREF_3 11 ...

  • Page 79

    ... They are sorted by bank number and then by the pin name of the largest device. Pins that form a differential I/O pair appear together in the table. The differential I/O pairs that have different assignments between the XC3S50AN and the XC3S200AN or XC3S400AN are highlighted in light blue in See ...

  • Page 80

    ... Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN, XC3S200AN, XC3S400AN) (Cont’d) Bank XC3S50AN Pin Name 0 N.C. 0 N.C. 0 IO_L15N_0 0 IO_L15P_0 0 IO_L16N_0 0 IO_L16P_0 0 IO_L17N_0 0 IO_L17P_0 0 IO_L18N_0 0 IO_L18P_0 0 IO_L19N_0 0 IO_L19P_0 0 IO_L20N_0/PUDC_B 0 IO_L20P_0/VREF_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0/VREF_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 1 IO_L01N_1/LDC2 1 IO_L01P_1/HDC 1 IO_L02N_1/LDC0 ...

  • Page 81

    ... Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN, XC3S200AN, XC3S400AN) (Cont’d) Bank XC3S50AN Pin Name 1 IO_L10P_1 1 IO_L11N_1/RHCLK1 1 IO_L11P_1/RHCLK0 1 IO_L12N_1/TRDY1/RHCLK3 1 IO_L12P_1/RHCLK2 1 IO_L14N_1/RHCLK5 1 IO_L14P_1/RHCLK4 1 IO_L15N_1/RHCLK7 1 IO_L15P_1/IRDY1/RHCLK6 1 N.C. 1 N.C. 1 N.C. 1 N.C. 1 N.C. 1 N.C. 1 N.C. 1 N.C. 1 IO_L20N_1 1 IO_L20P_1 1 IO_L22N_1 1 IO_L22P_1 1 IO_L23N_1 1 IO_L23P_1 1 IO_L24N_1 1 IO_L24P_1 1 IP_L04N_1/VREF_1 1 IP_L04P_1 1 N.C. ...

  • Page 82

    ... Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN, XC3S200AN, XC3S400AN) (Cont’d) Bank XC3S50AN Pin Name 2 IO_L01N_2/M0 2 IO_L01P_2/M1 2 IO_L02N_2/CSO_B 2 IO_L02P_2/M2 2 IO_L04P_2/VS2 2 IO_L03P_2/RDWR_B 2 IO_L04N_2/VS0 2 IO_L03N_2/VS1 2 IO_L06P_2 2 IO_L05P_2 2 IO_L06N_2/D6 2 IO_L05N_2/D7 2 N.C. 2 N.C. 2 IO_L08N_2/D4 2 IO_L08P_2/D5 2 N.C. 2 N.C. 2 IO_L10N_2/GCLK15 2 IO_L10P_2/GCLK14 2 IO_L11N_2/GCLK1 2 IO_L11P_2/GCLK0 2 IO_L12N_2/GCLK3 2 IO_L12P_2/GCLK2 2 N.C. 2 N.C. 2 IO_L14P_2/MOSI/CSI_B 2 IO_L14N_2 ...

  • Page 83

    ... Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN, XC3S200AN, XC3S400AN) (Cont’d) Bank XC3S50AN Pin Name 2 IP_2 2 IP_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 3 IO_L01N_3 3 IO_L01P_3 3 IO_L02N_3 3 IO_L02P_3 3 IO_L03N_3 3 IO_L03P_3 3 N.C. 3 N.C. 3 N.C. 3 N.C. 3 IO_L08N_3/VREF_3 3 IO_L08P_3 3 N.C. 3 N.C. 3 N.C. 3 N.C. ...

  • Page 84

    ... Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN, XC3S200AN, XC3S400AN) (Cont’d) Bank XC3S50AN Pin Name 3 N.C. 3 N.C. 3 N.C. 3 N.C. 3 IO_L20N_3 3 IO_L20P_3 3 IO_L22N_3 3 IO_L22P_3 3 IO_L23N_3 3 IO_L23P_3 3 IO_L24N_3 3 IO_L24P_3 3 IP_L04N_3/VREF_3 3 IP_L04P_3 3 N.C. 3 N.C. 3 IP_L13N_3 3 IP_L13P_3 3 IP_L21N_3 3 IP_L21P_3 3 IP_L25N_3/VREF_3 3 IP_L25P_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 GND GND ...

  • Page 85

    ... Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN, XC3S200AN, XC3S400AN) (Cont’d) Bank XC3S50AN Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...

  • Page 86

    ... Table 71: User I/Os Per Bank on XC3S50AN in the FTG256 Package Package I/O Bank Maximum I/Os Edge Top 0 Right 1 Bottom 2 Left 3 Total Table 72: User I/Os Per Bank on XC3S200AN and XC3S400AN in the FTG256 Package Package I/O Bank Maximum I/Os Edge Top 0 Right 1 Bottom 2 Left 3 Total DS557 (v4 ...

  • Page 87

    ... XC3S50AN and the XC3S200AN or XC3S400AN devices for migration between these devices in the FTG256 package. The XC3S200AN and XC3S400AN have identical pinouts. The XC3S50AN pinout is compatible with the XC3S200AN and XC3S400AN, however, there are 51 unconnected balls and one functionally different ball ...

  • Page 88

    ... XC3S200AN or XC3S400AN I/O I/O/VREF I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O/VREF I/O I/O I/O I/O I/O I/O I/O I/O ...

  • Page 89

    ... XC3S50AN Differential I/O Alignment Differences Also, some differential I/O pairs on the XC3S50AN FPGA are aligned differently than the corresponding pairs on the XC3S200AN or XC3S400AN FPGAs, as shown in pair is shaded. Table 74: Differential I/O Differences in FTG256 FTG256 Ball Bank P10 T10 R13 T14 XC3S50AN Does Not Have BPI Mode Address Outputs The XC3S50AN FPGA does not generate the BPI-mode address pins during configuration ...

  • Page 90

    FTG256 Footprint (XC3S50AN) (Differential Outputs I/O I/O A GND L19P_0 L18P_0 I/O I/O B TDI TMS L19N_0 L18N_0 I/O I/O I/O C GND L20P_0 L01N_3 L01P_3 VREF_0 I/O I/O I/O D VCCO_3 L03P_3 L02N_3 L02P_3 I/O ...

  • Page 91

    ... L02P_2 L03P_2 L23P_3 M2 RDWR_B I/O I/O I/O T GND L02N_2 L03N_2 L05P_2 CSO_B VS2 Figure 21: XC3S200AN and XC3S400AN FPGA in FTG256 Package Footprint (Top View) I/O: Unrestricted general-purpose user I/O INPUT: Unrestricted general-purpose input pin CONFIG: Dedicated 2 4 configuration pins N.C.: Not connected 0 28 DS557 (v4 ...

  • Page 92

    FGG400: 400-Ball Fine-Pitch Ball Grid Array The 400-ball fine-pitch ball grid array, FGG400, supports the XC3S400AN FPGA as shown in Table 76 lists all the FGG400 package pins. They are sorted by bank number and then by pin name. Pins ...

  • Page 93

    Table 76: Spartan-3AN FGG400 Pinout (Cont’d) Bank Pin Name 0 IO_L32N_0/PUDC_B 0 IO_L32P_0/VREF_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0 0 IP_0/VREF_0 0 ...

  • Page 94

    Table 76: Spartan-3AN FGG400 Pinout (Cont’d) Bank Pin Name 1 IO_L38P_1/A24 1 IP_1/VREF_1 1 IP_L04N_1/VREF_1 1 IP_L04P_1 1 IP_L11N_1/VREF_1 1 IP_L11P_1 1 IP_L15N_1 1 IP_L15P_1/VREF_1 1 IP_L19N_1 1 IP_L19P_1 1 IP_L23N_1 1 IP_L23P_1/VREF_1 1 IP_L27N_1 1 IP_L27P_1 1 IP_L31N_1 1 ...

  • Page 95

    Table 76: Spartan-3AN FGG400 Pinout (Cont’d) Bank Pin Name 2 IO_L28P_2 2 IO_L29N_2 2 IO_L29P_2 2 IO_L30N_2 2 IO_L30P_2 2 IO_L31N_2 2 IO_L31P_2 2 IO_L32N_2/CCLK 2 IO_L32P_2/D0/DIN/MISO 2 IP_2 2 IP_2 2 IP_2 2 IP_2 2 IP_2 2 IP_2 2 ...

  • Page 96

    Table 76: Spartan-3AN FGG400 Pinout (Cont’d) Bank Pin Name 3 IO_L34P_3 3 IO_L36N_3 3 IO_L36P_3 3 IO_L37N_3 3 IO_L37P_3 3 IO_L38N_3 3 IO_L38P_3 3 IP_3 3 IP_L04N_3/VREF_3 3 IP_L04P_3 3 IP_L11N_3/VREF_3 3 IP_L11P_3 3 IP_L15N_3 3 IP_L15P_3 3 IP_L19N_3 3 ...

  • Page 97

    Table 76: Spartan-3AN FGG400 Pinout (Cont’d) Bank Pin Name VCCAUX TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT ...

  • Page 98

    FGG400 Footprint X-Ref Target - Figure 22 Left Half of FGG400 Package (Top View) I/O: Unrestricted, 155 general-purpose user I/O INPUT: Unrestricted, 46 general-purpose input pin DUAL: Configuration pins, 51 then possible user I/O VREF: User I/O or input 26 ...

  • Page 99

    Bank I/O I/O I/O GND VCCAUX L13N_0 L07N_0 L08N_0 I/O I/O I/O I/O GND L14P_0 L13P_0 L11P_0 L08P_0 I/O I/O I/O I/O I/O L10N_0 L14N_0 L11N_0 L07P_0 L06N_0 VREF_0 I/O I/O I/O I/O VCCO_0 ...

  • Page 100

    FGG484: 484-Ball Fine-Pitch Ball Grid Array The 484-ball fine-pitch ball grid array, FGG484, supports both the XC3S700AN and the XC3S1400AN FPGAs. There are three pinout differences, as described in Table 78 lists all the FGG484 package pins. They are sorted ...

  • Page 101

    Table 78: Spartan-3AN FGG484 Pinout (Cont’d) Bank Pin Name 0 IO_L29N_0 0 IO_L29P_0 0 IO_L30N_0 0 IO_L30P_0 0 IO_L31N_0 0 IO_L31P_0 0 IO_L32N_0 0 IO_L32P_0 0 IO_L33N_0 0 IO_L33P_0 0 IO_L34N_0 0 IO_L34P_0 0 IO_L35N_0 0 IO_L35P_0 0 IO_L36N_0/PUDC_B 0 ...

  • Page 102

    Table 78: Spartan-3AN FGG484 Pinout (Cont’d) Bank Pin Name 1 IO_L25N_1/RHCLK7 1 IO_L25P_1/IRDY1/RHCLK6 1 IO_L26N_1/A11 1 IO_L26P_1/A10 1 IO_L28N_1 1 IO_L28P_1 1 IO_L29N_1/A13 1 IO_L29P_1/A12 1 IO_L30N_1/A15 1 IO_L30P_1/A14 1 IO_L32N_1 1 IO_L32P_1 1 IO_L33N_1/A17 1 IO_L33P_1/A16 1 IO_L34N_1/A19 1 ...

  • Page 103

    Table 78: Spartan-3AN FGG484 Pinout (Cont’d) Bank Pin Name 2 IO_L10N_2 2 IO_L10P_2 2 IO_L11N_2/VS0 2 IO_L11P_2/VS1 2 IO_L12N_2 2 IO_L12P_2 2 IO_L13N_2 2 IO_L13P_2 2 IO_L14N_2/D6 2 IO_L14P_2/D7 2 IO_L15N_2 2 IO_L15P_2 2 IO_L16N_2/D4 2 IO_L16P_2/D5 2 IO_L17N_2/GCLK13 2 ...

  • Page 104

    Table 78: Spartan-3AN FGG484 Pinout (Cont’d) Bank Pin Name 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 3 IO_L01N_3 3 IO_L01P_3 3 IO_L02N_3 3 IO_L02P_3 3 IO_L03N_3 3 IO_L03P_3 3 IO_L05N_3 3 IO_L05P_3 3 IO_L06N_3 3 ...

  • Page 105

    Table 78: Spartan-3AN FGG484 Pinout (Cont’d) Bank Pin Name 3 IP_L04N_3/VREF_3 3 IP_L04P_3 3 IP_L11N_3 3 IP_L11P_3 3 IP_L15N_3/VREF_3 3 IP_L15P_3 3 IP_L19N_3 3 IP_L19P_3 3 IP_L23N_3 3 IP_L23P_3 3 IP_L27N_3 3 IP_L27P_3 3 IP_L31N_3 3 IP_L31P_3 3 IP_L35N_3 3 ...

  • Page 106

    Table 78: Spartan-3AN FGG484 Pinout (Cont’d) Bank Pin Name VCCAUX DONE VCCAUX PROG_B VCCAUX TCK VCCAUX TDI VCCAUX TDO VCCAUX TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX ...

  • Page 107

    User I/Os by Bank Table 79 and Table 80 indicate how the user-I/O pins are distributed between the four I/O banks on the FGG484 package. The AWAKE pin is counted as a dual-purpose I/O. Table 79: User I/Os Per Bank ...

  • Page 108

    FGG484 Footprint X-Ref Target - Figure 23 Left Half of FGG484 Package (Top View) I/O: Unrestricted, general-purpose user I/O 195 INPUT: Unrestricted, 60- general-purpose input pin 62 DUAL: Configuration pins, then possible user I/O 51 VREF: User I/O or input ...

  • Page 109

    Bank I/O I/O I/O I/O I/O I/O L18P_0 L12N_0 L16N_0 L13N_0 L12P_0 L10N_0 GCLK6 VREF_0 I/O I/O I/O GND GND VCCO_0 L16P_0 L13P_0 L10P_0 I/O I/O I/O I/O I/O I/O L17P_0 L15N_0 L09P_0 ...

  • Page 110

    FGG676: 676-Ball Fine-Pitch Ball Grid Array The 676-ball fine-pitch ball grid array, FGG676, supports the XC3S1400AN FPGA. Table 82 lists all the FGG676 package pins. They are sorted by bank number and then by pin name. Pins that form a ...

  • Page 111

    Table 82: Spartan-3AN FGG676 Pinout (Cont’d) Bank Pin Name 0 IO_L33N_0 0 IO_L33P_0 0 IO_L34N_0 0 IO_L34P_0 0 IO_L35N_0 0 IO_L35P_0 0 IO_L36N_0 0 IO_L36P_0 0 IO_L37N_0 0 IO_L37P_0 0 IO_L38N_0 0 IO_L38P_0 0 IO_L39N_0 0 IO_L39P_0 0 IO_L40N_0 0 ...

  • Page 112

    Table 82: Spartan-3AN FGG676 Pinout (Cont’d) Bank Pin Name 1 IO_L02P_1/LDC1 1 IO_L03N_1/A1 1 IO_L03P_1/A0 1 IO_L04N_1 1 IO_L04P_1 1 IO_L05N_1 1 IO_L05P_1 1 IO_L06N_1 1 IO_L06P_1 1 IO_L07N_1/VREF_1 1 IO_L07P_1 1 IO_L08N_1 1 IO_L08P_1 1 IO_L09N_1 1 IO_L09P_1 1 ...

  • Page 113

    Table 82: Spartan-3AN FGG676 Pinout (Cont’d) Bank Pin Name 1 IO_L51P_1 1 IO_L53N_1 1 IO_L53P_1 1 IO_L54N_1 1 IO_L54P_1 1 IO_L55N_1 1 IO_L55P_1 1 IO_L56N_1 1 IO_L56P_1 1 IO_L57N_1 1 IO_L57P_1 1 IO_L58N_1 1 IO_L58P_1/VREF_1 1 IO_L59N_1 1 IO_L59P_1 1 ...

  • Page 114

    Table 82: Spartan-3AN FGG676 Pinout (Cont’d) Bank Pin Name 2 IO_L15N_2 2 IO_L15P_2 2 IO_L16N_2 2 IO_L16P_2 2 IO_L17N_2/VS2 2 IO_L17P_2/RDWR_B 2 IO_L18N_2 2 IO_L18P_2 2 IO_L19N_2/VS0 2 IO_L19P_2/VS1 2 IO_L20N_2 2 IO_L20P_2 2 IO_L21N_2 2 IO_L21P_2 2 IO_L22N_2/D6 2 ...

  • Page 115

    Table 82: Spartan-3AN FGG676 Pinout (Cont’d) Bank Pin Name 2 IP_2 2 IP_2 2 IP_2 2 IP_2 2 IP_2 2 IP_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 IP_2/VREF_2 2 ...

  • Page 116

    Table 82: Spartan-3AN FGG676 Pinout (Cont’d) Bank Pin Name 3 IO_L30N_3 3 IO_L30P_3 3 IO_L31N_3 3 IO_L31P_3 3 IO_L32N_3/LHCLK1 3 IO_L32P_3/LHCLK0 3 IO_L33N_3/IRDY2/LHCLK3 3 IO_L33P_3/LHCLK2 3 IO_L34N_3/LHCLK5 3 IO_L34P_3/LHCLK4 3 IO_L35N_3/LHCLK7 3 IO_L35P_3/TRDY2/LHCLK6 3 IO_L36N_3 3 IO_L36P_3/VREF_3 3 IO_L37N_3 3 ...

  • Page 117

    Table 82: Spartan-3AN FGG676 Pinout (Cont’d) Bank Pin Name 3 IP_L58N_3/VREF_3 3 IP_L58P_3 3 IP_L62N_3 3 IP_L62P_3 3 IP_L66N_3/VREF_3 3 IP_L66P_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 GND ...

  • Page 118

    Table 82: Spartan-3AN FGG676 Pinout (Cont’d) Bank Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX SUSPEND VCCAUX DONE VCCAUX PROG_B VCCAUX ...

  • Page 119

    User I/Os by Bank Table 83 indicates how the 502 available user-I/O pins are distributed between the four I/O banks on the FGG676 package. The AWAKE pin is counted as a dual-purpose I/O. Table 83: User I/Os Per Bank for ...

  • Page 120

    FGG676 Footprint X-Ref Target - Figure 24 Left Half of FGG676 Package (Top View) I/O: Unrestricted, 313 general-purpose user I/O INPUT: Unrestricted, general-purpose input pin 67 DUAL: Configuration pins, then possible user I/O 51 SUSPEND: Dedicated SUSPEND and 2 dual-purpose ...

  • Page 121

    Bank I/O I/O I/O I/O I/O GND INPUT L26N_0 L23N_0 L18N_0 L15N_0 L14N_0 GCLK7 I/O I/O I/O I/O I/O I/O VCCO_0 L26P_0 L14P_0 L23P_0 L19N_0 L18P_0 L15P_0 GCLK6 VREF_0 I/O I/O I/O ...

  • Page 122

    Revision History The following table shows the revision history for this document. Date Version 02/26/07 1.0 Initial release. 08/16/07 2.0 Updated for Production release of initial device. Noted that family is available in Pb-free packages only. 09/12/07 2.0.1 Minor updates ...

  • Page 123

    Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY ...