XC3S200AN-4FTG256C Xilinx Inc, XC3S200AN-4FTG256C Datasheet - Page 26

IC SPARTAN-3AN FPGA 200K 256FTBG

XC3S200AN-4FTG256C

Manufacturer Part Number
XC3S200AN-4FTG256C
Description
IC SPARTAN-3AN FPGA 200K 256FTBG
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr

Specifications of XC3S200AN-4FTG256C

Total Ram Bits
294912
Number Of Logic Elements/cells
4032
Number Of Labs/clbs
448
Number Of I /o
195
Number Of Gates
200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
No. Of Logic Blocks
4032
No. Of Gates
200000
No. Of Macrocells
4032
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
195
Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1553

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Pin-to-Pin Setup and Hold Times
Table 22: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
3.
4.
Setup Times
Hold Times
The numbers in this table are tested using the methodology presented in
Table 10
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from
appropriate Input adjustment from the same table.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
DCM output jitter is included in all measurements.
Symbol
T
T
T
T
PSDCM
PHDCM
PHFD
PSFD
and
Table
When writing to the Input
Flip-Flop (IFF), the time from the
setup of data at the Input pin to
the active transition at a Global
Clock pin. The DCM is in use. No
Input Delay is programmed.
When writing to IFF, the time from
the setup of data at the Input pin
to an active transition at the
Global Clock pin. The DCM is not
in use. The Input Delay is
programmed.
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is in use. No Input Delay is
programmed.
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is not in use. The Input
Delay is programmed.
13.
Description
LVCMOS25
IFD_DELAY_VALUE = 0,
with DCM
LVCMOS25
IFD_DELAY_VALUE = 5,
without DCM
LVCMOS25
IFD_DELAY_VALUE = 0,
with DCM
LVCMOS25
IFD_DELAY_VALUE = 5,
without DCM
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
Conditions
(4)
(4)
(2)
(2)
(3)
(3)
,
,
,
,
Table 30
and are based on the operating conditions set forth in
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
Table
Table
Device
26. If this is true of the data Input, add the
26. If this is true of the data Input, subtract the
–0.36
–0.52
–0.33
–0.17
–0.07
–0.63
–0.56
–0.42
–0.80
–0.69
2.45
2.59
2.38
2.38
1.91
2.55
2.32
2.21
2.28
2.33
Min
-5
Speed Grade
–0.36
–0.52
–0.29
–0.12
–0.58
–0.56
–0.42
–0.75
–0.69
2.68
2.84
2.68
2.57
2.17
2.76
2.76
2.60
2.63
2.41
0.00
Min
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
26

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