XC3S200AN-4FTG256C Xilinx Inc, XC3S200AN-4FTG256C Datasheet - Page 35

IC SPARTAN-3AN FPGA 200K 256FTBG

XC3S200AN-4FTG256C

Manufacturer Part Number
XC3S200AN-4FTG256C
Description
IC SPARTAN-3AN FPGA 200K 256FTBG
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr

Specifications of XC3S200AN-4FTG256C

Total Ram Bits
294912
Number Of Logic Elements/cells
4032
Number Of Labs/clbs
448
Number Of I /o
195
Number Of Gates
200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
No. Of Logic Blocks
4032
No. Of Gates
200000
No. Of Macrocells
4032
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
195
Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1553

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Input Timing Adjustments
Table 26: Input Timing Adjustments by IOSTANDARD
DS557 (v4.1) April 1, 2011
Product Specification
Single-Ended Standards
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
PCI66_3
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
Following Signal Standard
Convert Input Time from
LVCMOS25 to the
(IOSTANDARD)
Adjustment Below
0.62
0.54
0.83
0.60
0.31
0.41
0.41
0.72
0.77
0.69
0.69
0.79
0.71
0.71
0.68
0.68
0.78
0.78
-5
Speed Grade
0
Add the
0.69
0.69
0.62
0.54
0.83
0.60
0.31
0.41
0.41
0.72
0.77
0.79
0.71
0.71
0.68
0.68
0.78
0.78
-4
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
Table 26: Input Timing Adjustments by IOSTANDARD
Notes:
1.
2.
Differential Standards
LVDS_25
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
LVPECL_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
Following Signal Standard
Convert Input Time from
The numbers in this table are tested using the methodology
presented in
set forth in
These adjustments are used to convert input path times originally
specified for the LVCMOS25 standard to times that correspond to
other signal standards.
LVCMOS25 to the
(IOSTANDARD)
Table
Table 30
10,
Table
and are based on the operating conditions
13, and
Adjustment Below
0.76
0.79
0.79
0.78
0.79
0.78
0.79
0.79
0.77
0.79
0.79
0.79
0.74
0.72
1.05
0.72
1.05
0.71
0.71
0.74
0.75
1.06
1.06
-5
Speed Grade
Table
Add the
15.
0.76
0.79
0.79
0.78
0.79
0.78
0.79
0.79
0.77
0.79
0.79
0.79
0.74
0.72
1.05
0.72
1.05
0.71
0.71
0.74
0.75
1.06
1.06
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35

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