XC3S200AN-4FTG256C Xilinx Inc, XC3S200AN-4FTG256C Datasheet - Page 65

IC SPARTAN-3AN FPGA 200K 256FTBG

XC3S200AN-4FTG256C

Manufacturer Part Number
XC3S200AN-4FTG256C
Description
IC SPARTAN-3AN FPGA 200K 256FTBG
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr

Specifications of XC3S200AN-4FTG256C

Total Ram Bits
294912
Number Of Logic Elements/cells
4032
Number Of Labs/clbs
448
Number Of I /o
195
Number Of Gates
200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
No. Of Logic Blocks
4032
No. Of Gates
200000
No. Of Macrocells
4032
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
195
Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1553

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External Serial Peripheral Interface (SPI) Configuration Timing
X-Ref Target - Figure 16
Table 57: Timing for External Serial Peripheral Interface (SPI) Configuration Mode
DS557 (v4.1) April 1, 2011
Product Specification
(Open-Drain)
T
T
T
T
T
T
T
PROG_B
CCLK1
CCLKn
MINIT
INITM
CCO
DCC
CCD
PUDC_B
Symbol
VS[2:0]
CSO_B
INIT_B
M[2:0]
CCLK
(Input)
(Input)
(Input)
(Input)
(Input)
MOSI
DIN
Shaded values indicate specifications on attached SPI Flash PROM.
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate bitstream option setting
Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the
rising edge of INIT_B
Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the
rising edge of INIT_B
MOSI output valid delay after CCLK falling clock edge
Setup time on the DIN data input before CCLK rising clock edge
Hold time on the DIN data input after CCLK rising clock edge
Figure 16: Waveforms for External Serial Peripheral Interface (SPI) Configuration
T
MINIT
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.
<1:1:1>
<0:0:1>
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
T
INITM
T
CCLK1
Description
T
CSS
Command
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
(msb)
T
CCO
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
T
DSU
T
MCCL1
Command
(msb-1)
T
MCCH1
T
DH
Minimum
Data
50
0
T
T
New ConfigRate active
CCLK1
See
See
See
See
See
MCCL n
Data
T
T
Maximum
V
DCC
Table 51
Table 51
Table 55
Table 55
Table 55
Data
DS529-3_06_102506
T
T
CCLK n
T
CCD
MCCH n
Units
ns
ns
Data
65

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