XC3S200AN-4FTG256C Xilinx Inc, XC3S200AN-4FTG256C Datasheet - Page 73

IC SPARTAN-3AN FPGA 200K 256FTBG

XC3S200AN-4FTG256C

Manufacturer Part Number
XC3S200AN-4FTG256C
Description
IC SPARTAN-3AN FPGA 200K 256FTBG
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr

Specifications of XC3S200AN-4FTG256C

Total Ram Bits
294912
Number Of Logic Elements/cells
4032
Number Of Labs/clbs
448
Number Of I /o
195
Number Of Gates
200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
No. Of Logic Blocks
4032
No. Of Gates
200000
No. Of Macrocells
4032
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
195
Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1553

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Table 64: Maximum User I/O by Package
Electronic versions of the package pinout tables and foot-prints are available for download from the Xilinx website at:
Using a spreadsheet program, the data can be sorted and reformatted according to any specific needs. Similarly, the
ASCII-text file is easily parsed by most scripting programs.
Package Overview
Table 65
Table 65: Spartan-3AN Family Package Options
Each package style is available in an environmentally friendly lead-free (Pb-free) option. The Pb-free packages include an
extra “G” in the package style name. For example, the standard “CS484” package becomes “CSG484” when ordered as the
Pb-free option. Leaded (Pb) packages are available for selected devices, with the same pinout and without the “G” in the
ordering code; See
similar, as shown in the mechanical drawings provided in
For additional package information, see UG112: Device Package User Guide.
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
Notes:
1.
XC3S50AN
XC3S200AN
XC3S400AN
XC3S700AN
XC3S1400AN
TQ144/TQG144
FT256/FTG256
FG400/FGG400
FG484/FGG484
FG676/FGG676
http://www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip
Device
Some VREFs are on INPUT pins. See pinout tables for details.
For mass, refer to the MDDS files (see
Package
shows the five low-cost, space-saving production package styles for the Spartan-3AN family.
Package
TQG144
FGG400
FGG484
FGG484
FGG676
FTG256
FTG256
FTG256
Table 5, page 7
Leads
144
256
400
484
676
Input-Only
Thin Quad Flat Pack (TQFP)
Fine-pitch Thin Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Maximum
User I/Os
and
108
144
195
195
311
372
375
502
for more information. The mechanical dimensions of the Pb and Pb-free packages are
Table
Maximum
66).
Input-
Only
Type
32
35
35
63
84
87
94
7
Differential
www.xilinx.com
Maximum
Pairs
Table
142
165
165
227
50
64
90
90
66.
Maximum I/Os
155
194
195
313
I/O
42
53
69
69
Spartan-3AN FPGA Family: Pinout Descriptions
108
195
311
375
502
INPUT
20
21
21
46
61
62
67
2
All Possible I/Os by Type
Lead Pitch
DUAL
26
26
52
52
52
52
52
52
(mm)
0.5
1.0
1.0
1.0
1.0
VREF
15
21
21
26
33
34
38
8
Body Area
(1)
20 x 20
17 x 17
21 x 21
23 x 23
27 x 27
(mm)
CLK
30
30
32
32
32
32
32
32
Height
(mm)
1.60
1.55
2.43
2.60
2.60
N.C.
51
17
0
0
0
0
3
0
73

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