XC3S200AN-4FTG256C Xilinx Inc, XC3S200AN-4FTG256C Datasheet - Page 87

IC SPARTAN-3AN FPGA 200K 256FTBG

XC3S200AN-4FTG256C

Manufacturer Part Number
XC3S200AN-4FTG256C
Description
IC SPARTAN-3AN FPGA 200K 256FTBG
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr

Specifications of XC3S200AN-4FTG256C

Total Ram Bits
294912
Number Of Logic Elements/cells
4032
Number Of Labs/clbs
448
Number Of I /o
195
Number Of Gates
200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
No. Of Logic Blocks
4032
No. Of Gates
200000
No. Of Macrocells
4032
Family Type
Spartan-3AN
No. Of Speed Grades
4
No. Of I/o's
195
Package
256FTBGA
Family Name
Spartan®-3AN
Device Logic Units
4032
Device System Gates
200000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
195
Ram Bits
294912
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1553

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73
Footprint Migration Differences
Unconnected Balls on XC3S50AN
Table 73
XC3S400AN devices for migration between these devices in the FTG256 package. The XC3S200AN and XC3S400AN have
identical pinouts. The XC3S50AN pinout is compatible with the XC3S200AN and XC3S400AN, however, there are 51
unconnected balls and one functionally different ball. Generally, designs migrate upward from the XC3S50AN to either the
XC3S200AN or XC3S400AN. If using differential I/O, see
Table
In
right. Migration in the other direction is possible depending on how the pin is configured for the device on the right.
Table 73: FTG256 XC3S50AN Footprint Migration/Differences
DS557 (v4.1) April 1, 2011
Product Specification
Table
FTG256 Ball
75.
G13
G14
G16
A12
B12
D10
E10
E16
H13
F14
F15
F16
J10
J11
A7
C7
E2
E3
E7
G3
G4
G5
G6
H4
H5
H6
K4
F3
F8
J4
J6
73, the arrow () indicates that this pin can unconditionally migrate from the device on the left to the device on the
summarizes any footprint and functionality differences between the XC3S50AN and the XC3S200AN or
Bank
0
0
0
0
0
3
3
0
0
1
3
0
1
1
1
3
3
3
3
1
1
1
3
3
3
1
3
3
1
1
3
N.C.
N.C.
INPUT
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
XC3S50AN
www.xilinx.com
Table
74. If using the BPI configuration mode (parallel Flash), see
Spartan-3AN FPGA Family: Pinout Descriptions
Migration
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O/VREF
I/O/VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT/VREF
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT/VREF
INPUT
I/O
XC3S200AN or XC3S400AN
87

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