XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 131

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 15: BG560 Differential Pin Pair Summary
XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E
DS022-4 (v2.5) March 14, 2003
Production Product Specification
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. AO in the XCV400E, 600E, 1000E, 2000E.
11. AO in the XCV400E, 600E, 1000E.
12. AO in the XCV400E, 1000E, 2000E.
13. AO in the XCV400E, 600E, 1000E, 1600E.
14. AO in the XCV400E, 1000E, 1600E.
15. AO in the XCV600E, 1000E, 2000E.
16. AO in the XCV600E, 2000E.
17. AO in the XCV400E, 600E, 1600E, 2000E.
18. AO in the XCV600E, 1000E, 1600E, 2000E.
19. AO in the XCV400E, 600E, 2000E.
20. AO in the XCV400E, 1000E.
Pair
171
172
173
174
175
176
177
178
179
180
181
182
AO in the XCV1600E.
AO in the XCV2000E.
AO in the XCV1600E, 2000E.
AO in the XCV1000E, 1600E.
AO in the XCV1000E, 2000E.
AO in the XCV1000E.
AO in the XCV1000E, 1600E, 2000E.
AO in the XCV600E, 1600E.
AO in the XCV400E, 600E, 1600E.
Bank
7
7
7
7
7
7
7
7
7
7
7
7
R
G32
G31
K31
H33
H32
H31
E32
E31
C33
D31
F31
Pin
J33
P
M29
H29
D32
G29
K29
E33
F30
L30
L29
J31
J30
J29
Pin
N
AO
18
14
20
15
14
15
14
14
√
√
4
√
Functions
Other
VREF
VREF
VREF
VREF
VREF
VREF
-
-
-
-
-
-
www.xilinx.com
1-800-255-7778
FG256 Fine-Pitch Ball Grid Array Packages
XCV50E, XCV100E, XCV200E, and XCV300E devices in
FG256 fine-pitch Ball Grid Array packages have footprint
compatibility. Pins labeled I0_VREF can be used as either
in all parts unless device-dependent as indicated in the foot-
notes. If the pin is not used as V
eral I/O. Immediately following
Differential Pair information.
Table 16: FG256 Package — XCV50E, XCV100E,
XCV200E, XCV300E
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Virtex™-E 1.8 V Field Programmable Gate Arrays
IO_LVDS_DLL_L8N
IO_LVDS_DLL_L8P
IO_VREF_L2N_YY
IO_VREF_L4N_YY
IO_VREF_L10P_Y
IO_VREF_L7N_Y
IO_VREF_L0P_Y
Pin Description
IO_L1N_YY
IO_L1P_YY
IO_L2P_YY
IO_L4P_YY
IO_L5N_YY
IO_L5P_YY
IO_L10N_Y
IO_L0N_Y
IO_L3N_Y
IO_L6N_Y
IO_L9N_Y
IO_L3P_Y
IO_L6P_Y
IO_L7P_Y
IO_L9P_Y
GCK3
GCK2
IO
IO
IO
IO
REF
Table
, it can be used as gen-
16, see
Module 4 of 4
Table 17
Pin #
C6
B10
E10
A3
B8
B3
E7
D8
C5
D5
E6
B4
A4
D6
B5
A5
B6
C7
D7
C8
B7
A6
A7
C9
A8
D9
A9
B9
2
1
for
45