XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 44

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
IOB Flip-Flop/Latch Property
The Virtex-E series I/O Block (IOB) includes an optional
register on the input path, an optional register on the output
path, and an optional register on the 3-state control pin. The
design implementation software automatically takes advan-
tage of these registers when the following option for the Map
program is specified.
map –pr b <filename>
Alternatively, the IOB = TRUE property can be placed on a
register to force the mapper to place the register in an IOB.
Location Constraints
Specify the location of each SelectI/O symbol with the loca-
tion constraint LOC attached to the SelectI/O symbol. The
external port identifier indicates the value of the location
constrain. The format of the port identifier depends on the
package chosen for the specific design.
The LOC properties use the following form:
Output Slew Rate Property
As mentioned above, a variety of symbol names provide the
option of choosing the desired slew rate for the output buff-
ers. In the case of the LVTTL output buffers (OBUF, OBUFT,
and IOBUF), slew rate control can be alternatively pro-
gramed with the SLEW= property. By default, the slew rate
for each output buffer is reduced to minimize power bus
transients when switching non-critical signals. The SLEW=
property has one of the two following values.
Output Drive Strength Property
The desired output drive strength can be additionally speci-
fied by choosing the appropriate library symbol. The Xilinx
library also provides an alternative method for specifying
this feature. For the LVTTL output buffers (OBUF, OBUFT,
and IOBUF, the desired drive strength can be specified with
the DRIVE= property. This property could have one of the
following seven values.
Module 2 of 4
38
LOC=A42
LOC=P37
SLEW=SLOW
SLEW=FAST
DRIVE=2
DRIVE=4
DRIVE=6
DRIVE=8
DRIVE=12 (Default)
DRIVE=16
DRIVE=24
www.xilinx.com
Design Considerations
Reference Voltage (V
Low-voltage I/O standards with a differential amplifier input
buffer require an input reference voltage (V
V
The voltage reference signal is “banked” within the device on
a half-edge basis such that for all packages there are eight
independent V
resentation of the Virtex-E I/O banks. Within each bank
approximately one of every six I/O pins is automatically con-
figured as a V
input signal within a given V
source must drive all I/O pins configured as a V
Within each V
V
type and input buffers can be placed without requiring a ref-
erence voltage within the same V
Output Drive Source Voltage (V
Many of the low voltage I/O standards supported by
SelectI/O devices require a different output drive source
voltage (V
support multiple output drive source voltages.
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four V
Output buffers within a given V
same output drive source voltage. Input buffers for LVTTL,
LVCMOS2, LVCMOS18, PCI33_3, and PCI 66_3 use the
V
Transmission Line Effects
The delay of an electrical signal along a wire is dominated
by the rise and fall times when the signal travels a short dis-
tance. Transmission line delays vary with inductance and
capacitance, but a well-designed board can experience
delays of approximately 180 ps per inch.
Transmission line effects, or reflections, typically start at
1.5" for fast (1.5 ns) rise and fall times. Poor (or non-exis-
tent) termination or changes in the transmission line imped-
ance cause these reflections and can cause additional
delay in longer traces. As system speeds continue to
increase, the effect of I/O delays can become a limiting fac-
tor and therefore transmission line termination becomes
increasingly more important.
Termination Techniques
A variety of termination techniques reduce the impact of
transmission line effects.
The following are output termination techniques:
•
•
•
•
REF
REF
CCO
None
Series
Parallel (Shunt)
Series and Parallel (Series-Shunt)
signal must be of the same type. Output buffers of any
as an external signal to the device.
voltage for Input V
CCO
REF
). As a result each device can often have to
REF
REF
input. After placing a differential amplifier
banks internally. See
bank, any input buffers that require a
CCO
REF
Production Product Specification
) Pins
voltage.
DS022-2 (v2.8) January 16, 2006
REF
CCO
REF
bank, the same external
CCO
bank.
bank must share the
Figure 38
) Pins
REF
CCO
). Provide the
REF
banks.
for a rep-
input.
R