XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 52

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
LVDS
Depending on whether the device is transmitting an LVDS
signal or receiving an LVDS signal, there are two different
circuits used for LVDS termination. A sample circuit illustrat-
ing a valid termination technique for transmitting LVDS sig-
nals appears in
valid termination for receiving LVDS signals appears in
Figure
information on the specific termination resistor packs shown
can be found on
Table 38: LVDS Voltage Specifications
Module 2 of 4
46
Notes:
1.
2.
V
V
V
V
V
V
V
OCM
ODIFF
OH
OL
Parameter
CCO
ICM
IDIFF
Measured with a 100 Ω resistor across Q and Q.
Measured with a differential input voltage = +/− 350 mV.
(1)
(1)
Figure 54: Transmitting LVDS Signal Circuit
(2)
(1)
55.
Figure 55: Receiving LVDS Signal Circuit
(1)
(1)
Virtex-E
Transmit
FPGA
DATA
Table 38
V
CCO
LVDS
Driver
from
Output
LVDS
2.5V
= 2.5V
Table
Figure
Q
Q
2.375
1.125
lists DC voltage specifications. Further
0.25
1.25
Min
Z 0 = 50Ω
Z 0 = 50Ω
0.2
0.1
Q
Q
-
40.
CAT16-LV4F12
54. A sample circuit illustrating a
1/4 of Bourns
Part Number
165
165
R
R
S
S
LVDS_IN
LVDS_IN
R DIV
140
R
100Ω
T
1.25
1.25
0.35
0.35
Z 0 = 50Ω
Z 0 = 50Ω
Typ
2.5
+
–
-
-
VIRTEX-E
FPGA
x133_29_122799
Receive
DATA
to LVDS Receiver
to LVDS Receiver
x133_19_122799
2.625
1.375
Max
0.45
1.25
2.2
-
-
www.xilinx.com
LVPECL
Depending on whether the device is transmitting or receiv-
ing an LVPECL signal, two different circuits are used for
LVPECL termination. A sample circuit illustrating a valid ter-
mination technique for transmitting LVPECL signals
appears in
mination for receiving LVPECL signals appears in
Figure
information on the specific termination resistor packs shown
can be found on
Table 39: LVPECL Voltage Specifications
Notes:
1.
V
V
V
V
V
V
V
OH
OL
CCO
REF
TT
IH
IL
Parameter
Figure 56: Transmitting LVPECL Signal Circuit
For more detailed information, see DS022-3: Virtex-E 1.8V
FPGA DC and Switching Characteristics, Module 3, LVPECL
DC Specifications section.
Figure 57: Receiving LVPECL Signal Circuit
57.
Virtex-E
Transmit
FPGA
DATA
Table 39
Figure
3.3V
LVPECL
Driver
from
Table
56. A sample circuit illustrating a valid ter-
Q
Q
Q
Q
lists DC voltage specifications. Further
1.49
0.86
CAT16-PC4F12
Min
1/4 of Bourns
Part Number
3.0
1.8
100
100
R
R
Z 0 = 50Ω
Z 0 = 50Ω
40.
S
S
-
-
-
R DIV
187
Production Product Specification
LVPECL_IN
LVPECL_IN
DS022-2 (v2.8) January 16, 2006
Z 0 = 50Ω LVPECL_OUT
Z 0 = 50Ω
R
100Ω
T
LVPECL_OUT
Typ
3.3
+
–
-
-
-
-
-
-
VIRTEX-E
FPGA
x133_21_122799
Receive
DATA
to LVPECL Receiver
to LVPECL Receiver
x133_20_122799
2.125
Max
2.72
1.57
3.6
-
-
-
R