XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 32

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
Data Output Bus—DO[A|B]<#:0>
The data out bus reflects the contents of the memory cells
referenced by the address bus at the last active clock edge.
During a write operation, the data out bus reflects the data
in bus. The width of this bus equals the width of the port.
The allowed widths appear in
Inverting Control Pins
The four control pins (CLK, EN, WE and RST) for each port
have independent inversion control as a configuration
option.
Address Mapping
Each port accesses the same set of 4096 memory cells
using an addressing scheme dependent on the width of the
port.
The physical RAM location addressed for a particular width
are described in the following formula (of interest only when
the two ports use different aspect ratios).
Conflict Resolution
The block SelectRAM+ memory is a true dual-read/write
port RAM that allows simultaneous access of the same
memory cell from both ports. When one port writes to a
given memory cell, the other port must not address that
memory cell (for a write or a read) within the clock-to-clock
setup window. The following lists specifics of port and mem-
ory cell write conflict resolution.
•
•
Conflicts do not cause any physical damage.
Module 2 of 4
26
Start = ((ADDR
End = ADDR
If both ports write to the same memory cell
simultaneously, violating the clock-to-clock setup
requirement, consider the data stored as invalid.
If one port attempts a read of the same memory cell
the other simultaneously writes, violating the
clock-to-clock setup requirement, the following occurs.
-
-
-
The write succeeds
The data out on the writing port accurately reflects
the data written.
The data out on the reading port is invalid.
port
port
* Width
+1) * Width
port
Table
port
15.
) –1
www.xilinx.com
Table 16
width.
Table 16: Port Address Mapping
Creating Larger RAM Structures
The block SelectRAM+ columns have specialized routing to
allow cascading blocks together with minimal routing delays.
This achieves wider or deeper RAM structures with a smaller
timing penalty than when using normal routing channels.
Location Constraints
Block SelectRAM+ instances can have LOC properties
attached to them to constrain the placement. The block
SelectRAM+ placement locations are separate from the
CLB location naming convention, allowing the LOC proper-
ties to transfer easily from array to array.
The LOC properties use the following form.
RAMB4_R0C0 is the upper left RAMB4 location on the
device.
Single Port Timing
Figure 33
SelectRAM+ memory. The block SelectRAM+ AC switching
characteristics are specified in the data sheet. The block
SelectRAM+ memory is initially disabled.
At the first rising edge of the CLK pin, the ADDR, DI, EN,
WE, and RST pins are sampled. The EN pin is High and the
WE pin is Low indicating a read operation. The DO bus con-
tains the contents of the memory location, 0x00, as indi-
cated by the ADDR bus.
At the second rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN and WE pins
are High indicating a write operation. The DO bus mirrors the
DI bus. The DI bus is written to the memory location 0x0F.
At the third rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is High
and the WE pin is Low indicating a read operation. The DO
bus contains the contents of the memory location 0x7E as
indicated by the ADDR bus.
At the fourth rising edge of the CLK pin, the ADDR, DI, EN,
WR, and RST pins are sampled again. The EN pin is Low
Width
Port
16
1
2
4
8
LOC = RAMB4_R#C#
shows low order address mapping for each port
4095...
2047...
1023...
shows a timing diagram for a single port of a block
511...
255...
1
5
07
1
4
03
1
3
06
1
2
01
Production Product Specification
1
1
Addresses
DS022-2 (v2.8) January 16, 2006
05
1
0
02
Port
0
9
04
0
8
00
0
7
03
0
6
01
0
5
02
0
4
00
0
3
01
0
2
00
0
1
00
0
0
R