XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 33

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

indicating that the block SelectRAM+ memory is now dis-
abled. The DO bus retains the last value.
Dual Port Timing
Figure 34
read/write block SelectRAM+ memory. The clock on port A
has a longer period than the clock on Port B. The timing
parameter T
diagram. The parameter, T
gram. All other timing parameters are identical to the single
port version shown in
T
are the same and at least one port is performing a write
operation. When the clock-to-clock set-up parameter is vio-
lated for a WRITE-WRITE condition, the contents of the
memory at that location are invalid. When the clock-to-clock
set-up parameter is violated for a WRITE-READ condition,
DS022-2 (v2.8) January 16, 2006
Production Product Specification
BCCS
is only of importance when the address of both ports
shows a timing diagram for a true dual-port
R
BCCS
, (clock-to-clock set-up) is shown on this
Figure
Figure 33: Timing Diagram for Single Port Block SelectRAM+ Memory
ADDR
DOUT
BCCS
RST
CLK
DIN
WE
EN
33.
DISABLED
is violated once in the dia-
T
T
T
T
BPWH
BACK
BDCK
BECK
DDDD
T
00
BCKO
READ
T
BWCK
MEM (00)
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CCCC
0F
WRITE
CCCC
the contents of the memory are correct, but the read port
has invalid data.
At the first rising edge of the CLKA, memory location 0x00 is
to be written with the value 0xAAAA and is mirrored on the
DOA bus. The last operation of Port B was a read to the
same memory location 0x00. The DOB bus of Port B does
not change with the new value on Port A, and retains the
last read value. A short time later, Port B executes another
read to memory location 0x00, and the DOB bus now
reflects the new memory value written by Port A.
At the second rising edge of CLKA, memory location 0x7E
is written with the value 0x9999 and is mirrored on the DOA
bus. Port B then executes a read operation to the same
memory location without violating the T
the DOB reflects the new memory values written by Port A.
T
BPWL
Virtex™-E 1.8 V Field Programmable Gate Arrays
BBBB
7E
READ
MEM (7E)
ds022_0343_121399
DISABLED
2222
8F
BCCS
parameter and
Module 2 of 4
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