XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 21

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

At power-up, V
than 50 ms, otherwise delay configuration by pulling
PROGRAM Low until V
SelectMAP Mode
The SelectMAP mode is the fastest configuration option.
Byte-wide data is written into the FPGA with a BUSY flag
controlling the flow of data.
An external data source provides a byte stream, CCLK, a
Chip Select (CS) signal and a Write signal (WRITE). If
BUSY is asserted (High) by the FPGA, the data must be
held until BUSY goes Low.
Data can also be read using the SelectMAP mode. If
WRITE is not asserted, configuration data is read out of the
FPGA as part of a readback operation.
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained to permit high-speed 8-bit readback.
Retention of the SelectMAP port is selectable on a
design-by-design basis when the bitstream is generated. If
retention is selected, PROHIBIT constraints are required to
prevent the SelectMAP-port pins from being used as user
I/O.
DS022-2 (v2.8) January 16, 2006
Production Product Specification
Figure 15: Serial Configuration Flowchart
FPGA checks data using CRC
FPGA enters start-up phase
and pulls INIT Low on error.
clearing pass and releases
causing DONE to go High.
If no CRC errors found,
configuration memory.
Serial Data In
Serial DOUT
FPGA starts to clear
FPGA makes a final
Once per bitstream,
R
INIT when finished.
(Output)
(Output)
CC
CCLK
must rise from 1.0 V to V
Figure 16: Master-Serial Mode Programming Switching Characteristics
CC
is valid.
Configuration Completed
Load a Configuration Bit
Set PROGRAM = High
Apply Power
Release INIT
Bitstream?
T CKDS
End of
INIT?
1 T DSCK
High
Yes
Low
No
2
If used to delay
configuration
ds009_15_111799
CC
Min in less
www.xilinx.com
Figure 16
Master-serial mode is selected by a <000> or <100> on the
mode pins (M2, M1, M0).
mation for
Multiple Virtex-E FPGAs can be configured using the
SelectMAP mode, and be made to start-up simultaneously.
To configure multiple devices in this way, wire the individual
CCLK, Data, WRITE, and BUSY pins of all the devices in
parallel. The individual devices are loaded separately by
asserting the CS pin of each device in turn and writing the
appropriate data. See
Characteristics.
Write
Write operations send packets of configuration data into the
FPGA. The sequence of operations for a multi-cycle write
operation is shown below. Note that a configuration packet
can be split into many such sequences. The packet does
not have to complete within one assertion of CS, illustrated
in
1. Assert WRITE and CS Low. Note that when CS is
2. Drive data onto D[7:0]. Note that to avoid contention,
Figure
asserted on successive CCLKs, WRITE must remain
either asserted or de-asserted. Otherwise, an abort is
initiated, as described below.
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more that one CS should be asserted.
Virtex™-E 1.8 V Field Programmable Gate Arrays
17.
shows the timing of master-serial configuration.
Figure
16.
Table 11
Table 10
for SelectMAP Write Timing
shows the timing infor-
DS022_44_071201
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