XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 14

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
The DLL also operates as a clock mirror. By driving the out-
put from a DLL off-chip and then back on again, the DLL can
be used to deskew a board level clock among multiple
devices.
To guarantee that the system clock is operating correctly
prior to the FPGA starting up after configuration, the DLL
can delay the completion of the configuration process until
after it has achieved lock. For more information about DLL
functionality, see the Design Consideration section of the
data sheet.
Boundary Scan
Virtex-E devices support all the mandatory Boundary Scan
instructions specified in the IEEE standard 1149.1. A Test
Access Port (TAP) and registers are provided that imple-
ment the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,
IDCODE, USERCODE, and HIGHZ instructions. The TAP
Module 2 of 4
8
Figure 10: DLL Locations
DLLDLL
DLLDLL
Primary DLLs
DLLDLL
DLLDLL
XCVE_0010
www.xilinx.com
also supports two internal scan chains and configura-
tion/readback of the device.
The JTAG input pins (TDI, TMS, TCK) do not have a V
requirement and operate with either 2.5 V or 3.3 V input sig-
nalling levels. The output pin (TDO) is sourced from the
V
els, the bank should be supplied with 3.3 V.
Boundary Scan operation is independent of individual IOB
configurations, and unaffected by package type. All IOBs,
including un-bonded ones, are treated as independent
3-state bidirectional pins in a single scan chain. Retention of
the bidirectional test capability after configuration facilitates
the testing of external interconnections, provided the user
design or application is turned off.
Table 6
Virtex-E FPGAs. Internal signals can be captured during
EXTEST by connecting them to un-bonded or unused IOBs.
They can also be connected to the unused outputs of IOBs
defined as unidirectional input pins.
Before the device is configured, all instructions except
USER1 and USER2 are available. After configuration, all
instructions are available. During configuration, it is recom-
mended that those operations using the Boundary Scan
register (SAMPLE/PRELOAD, INTEST, EXTEST) not be
performed.
In addition to the test instructions outlined above, the
Boundary Scan circuitry can be used to configure the
FPGA, and also to read back the configuration data.
Figure 11
Scan logic. It includes three bits of Data Register per IOB,
the IEEE 1149.1 Test Access Port controller, and the
Instruction Register with decodes.
CCO
in bank 2, and for proper operation of LVTTL 3.3 V lev-
lists the Boundary Scan instructions supported in
is a diagram of the Virtex-E Series Boundary
Production Product Specification
DS022-2 (v2.8) January 16, 2006
CCO
R