XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 39

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

standard requires a Differential Amplifier input buffer and a
Push-Pull output buffer.
SSTL3 — Stub Series Terminated Logic for 3.3V
The Stub Series Terminated Logic for 3.3V, or SSTL3 stan-
dard is a general purpose 3.3V memory bus standard also
sponsored by Hitachi and IBM (JESD8-8). This standard
has two classes, I and II. SelectI/O devices support both
classes for the SSTL3 standard. This standard requires a
Differential Amplifier input buffer and an Push-Pull output
buffer.
SSTL2 — Stub Series Terminated Logic for 2.5V
The Stub Series Terminated Logic for 2.5V, or SSTL2 stan-
dard is a general purpose 2.5V memory bus standard spon-
sored by Hitachi and IBM (JESD8-9). This standard has two
classes, I and II. SelectI/O devices support both classes for
the SSTL2 standard. This standard requires a Differential
Amplifier input buffer and an Push-Pull output buffer.
CTT — Center Tap Terminated
The Center Tap Terminated, or CTT standard is a 3.3V
memory bus standard sponsored by Fujitsu (JESD8-4).
This standard requires a Differential Amplifier input buffer
and a Push-Pull output buffer.
AGP-2X — Advanced Graphics Port
The Intel AGP standard is a 3.3V Advanced Graphics
Port-2X bus standard used with the Pentium II processor for
graphics applications. This standard requires a Push-Pull
output buffer and a Differential Amplifier input buffer.
LVDS — Low Voltage Differential Signal
LVDS is a differential I/O standard. It requires that one data
bit is carried through two signal lines. As with all differential
signaling standards, LVDS has an inherent noise immunity
over single-ended I/O standards. The voltage swing
between two signal lines is approximately 350mV. The use
of a reference voltage (V
(V
input or output. LVDS requires external resistor termination.
BLVDS — Bus LVDS
This standard allows for bidirectional LVDS communication
between two or more devices. The external resistor termi-
nation is different than the one for standard LVDS.
LVPECL — Low Voltage Positive Emitter Coupled
Logic
LVPECL is another differential I/O standard. It requires two
signal lines for transmitting one data bit. This standard
specifies two pins per input or output. The voltage swing
between these two signal lines is approximately 850 mV.
The use of a reference voltage (V
tion voltage (V
requires external resistor termination.
DS022-2 (v2.8) January 16, 2006
Production Product Specification
TT
) is not required. LVDS requires the use of two pins per
R
TT
) is not required. The LVPECL standard
REF
) or a board termination voltage
REF
) or a board termina-
www.xilinx.com
Library Symbols
The Xilinx library includes an extensive list of symbols
designed to provide support for the variety of SelectI/O fea-
tures. Most of these symbols represent variations of the five
generic SelectI/O symbols.
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IBUF
Signals used as inputs to the Virtex-E device must source
an input buffer (IBUF) via an external input port. The generic
Virtex-E IBUF symbol appears in
to the base name defines which I/O standard the IBUF
uses. The assumed standard is LVTTL when the generic
IBUF has no specified extension.
The following list details the variations of the IBUF symbol:
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•
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When the IBUF symbol supports an I/O standard that
requires a V
ferential amplifier input buffer. The V
supplied on the V
and BLVDS, V
IBUF (input buffer)
IBUFG (global clock input buffer)
OBUF (output buffer)
OBUFT (3-state output buffer)
IOBUF (input/output buffer)
IBUF
IBUF_LVCMOS2
IBUF_PCI33_3
IBUF_PCI66_3
IBUF_GTL
IBUF_GTLP
IBUF_HSTL_I
IBUF_HSTL_III
IBUF_HSTL_IV
IBUF_SSTL3_I
IBUF_SSTL3_II
IBUF_SSTL2_I
IBUF_SSTL2_II
IBUF_CTT
IBUF_AGP
IBUF_LVCMOS18
IBUF_LVDS
IBUF_LVPECL
Virtex™-E 1.8 V Field Programmable Gate Arrays
Figure 37: Input Buffer (IBUF) Symbols
REF
REF
, the IBUF automatically configures as a dif-
REF
is not required.
I
pins. In the case of LVDS, LVPECL,
IBUF
x133_01_111699
Figure
O
REF
37. The extension
voltage must be
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