XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 59

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS022-2 (v2.8) January 16, 2006
Production Product Specification
11/20/00
07/23/01
11/09/01
07/17/02
09/10/02
11/19/02
06/15/04
01/12/06
01/16/06
9/20/00
2/12/01
4/02/01
4/19/01
Date
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2.1
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Min values added to Virtex-E Electrical Characteristics tables.
Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to
Revised footnote for Table 14.
Updated numerous values in Virtex-E Switching Characteristics tables.
Modified
Made minor edits to text under Configuration.
Added warning under
Data sheet designation upgraded from Preliminary to Production.
Added clarification to the
Added clarification in the
Updated clickable web addresses.
Updated the
Made minor updates to
XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics
tables (Module 3).
Corrected user I/O count for XCV100E device in Table 1 (Module 1).
Changed several pins to “No Connect in the XCV100E“ and removed duplicate V
pins in Table ~ (Module 4).
Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4).
Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4).
Corrected pair 18 in Table 75 (Module 4) to be “AO in the XCV1000E, XCV1600E“.
Preliminary.
Updated minimums in Table 13 and added notes to Table 14.
Added to note 2 to Absolute Maximum Ratings.
Changed speed grade -8 numbers for T
Changed all minimum hold times to –0.4 under Global Clock Set-Up and Hold for
LVTTL Standard, with DLL.
Revised maximum T
Changed GCLK0 to BA22 for FG860 package in Table 46.
Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and
XCV2000E devices.
Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices.
Revised Table 62 to include pinout information for the XCV400E and XCV600E
devices in the BG560 package.
Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices.
Converted data sheet to modularized format. See the
Added CLB column locations for XCV2600E anbd XCV3200E devices in
bitstream causes configuration to fail and can damage the device.
Mode, and
Removed last sentence regarding deactivation of duty-cycle correction in
Correction Property
Figure 30
Block SelectRAM
Slave-Serial Mode
www.xilinx.com
"DLL Generation of 4x Clock in Virtex-E Devices."
DLLPW
section.
Configuration
Table
Boundary Scan
Input/Output
in -6 speed grade for DLL Timing Parameters.
8.
sections. Revised
and the
Virtex™-E 1.8 V Field Programmable Gate Arrays
Revision
section that attempting to load an incorrect
SHCKO32
Block, Configuration,
Master-Serial Mode
section.
, T
Figure
REG
Virtex-E Data Sheet
, T
18,
BCCS
Table
, and T
sections.
Boundary Scan
11, and
ICKOF
Table
Duty Cycle
Table
.
Module 2 of 4
section.
3.
CCINT
36.
53