XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 24

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
Configuration through the TAP uses the CFG_IN instruc-
tion. This instruction allows data input on TDI to be con-
verted into data packets for the internal configuration bus.
The following steps are required to configure the FPGA
through the Boundary Scan port (when using TCK as a
start-up clock).
1. Load the CFG_IN instruction into the Boundary Scan
2. Enter the Shift-DR (SDR) state.
3. Shift a configuration bitstream into TDI.
4. Return to Run-Test-Idle (RTI).
5. Load the JSTART instruction into IR.
6. Enter the SDR state.
7. Clock TCK through the startup sequence.
8. Return to RTI.
The corresponding timing characteristics are listed in
Table
Table 12: Power-up Timing Characteristics
Module 2 of 4
18
Notes:
1.
Program Pulse Width
CCLK (output) Delay
Power-on Reset
Program Latency
instruction register (IR).
T
V
POR
12.
CCO
Description
delay is the initialization time required after V
in Bank 2 reach the recommended operating voltage.
1
PROGRAM
T
Symbol
PROGRAM
T
T
Vcc
T
INIT
ICCK
POR
PL
Figure 20: Power-Up Timing Configuration Signals
Value
100.0
300
2.0
0.5
4.0
ms, max
μ
μ
CCINT
ns, min
μ
Units
s, max
s, max
s, min
CCLK OUTPUT or INPUT
www.xilinx.com
TPOR
and
M0, M1, M2
(Required)
TPL
Configuration and readback via the TAP is always available.
The Boundary Scan mode is selected by a <101> or <001>
on the mode pins (M2, M1, M0). For details on TAP charac-
teristics, refer to XAPP139.
Configuration Sequence
The configuration of Virtex-E devices is a three-phase pro-
cess. First, the configuration memory is cleared. Next, con-
figuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.
Configuration is automatically initiated on power-up unless
it is delayed by the user, as described below. The configura-
tion process can also be initiated by asserting PROGRAM.
The end of the memory-clearing phase is signalled by INIT
going High, and the completion of the entire process is sig-
nalled by DONE going High.
The power-up timing of configuration signals is shown in
Figure
Delaying Configuration
INIT can be held Low using an open-drain driver. An
open-drain is required since INIT is a bidirectional
open-drain pin that is held Low by the FPGA while the con-
figuration memory is being cleared. Extending the time that
the pin is Low causes the configuration sequencer to wait.
Thus, configuration is delayed by preventing entry into the
phase where data is loaded.
Start-Up Sequence
The default Start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary.
One CCLK cycle later, the Global Set/Reset (GSR) and Glo-
bal Write Enable (GWE) signals are released. This permits
20.
TICCK
VALI
ds022_020_071201
Production Product Specification
DS022-2 (v2.8) January 16, 2006
R