XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 7

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS022-2 (v2.8) January 16, 2006
Architectural Description
Virtex-E Array
The Virtex-E user-programmable gate array, shown in
Figure
figurable logic blocks (CLBs) and input/output blocks (IOBs).
•
•
CLBs interconnect through a general routing matrix (GRM).
The GRM comprises an array of routing switches located at
the intersections of horizontal and vertical routing channels.
Each CLB nests into a VersaBlock™ that also provides local
routing resources to connect the CLB to the GRM.
The VersaRing™ I/O interface provides additional routing
resources around the periphery of the device. This routing
improves I/O routability and facilitates pin locking.
The Virtex-E architecture also includes the following circuits
that connect to the GRM.
•
•
•
DS022-2 (v2.8) January 16, 2006
Production Product Specification
© 2000–2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
CLBs provide the functional elements for constructing
logic
IOBs provide the interface between the package pins
and the CLBs
Dedicated block memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
3-State buffers (BUFTs) associated with each CLB that
drive dedicated segmentable horizontal routing
resources
1, comprises two major configurable elements: con-
Figure 1: Virtex-E Architecture Overview
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DLLDLL
DLLDLL
VersaRing
VersaRing
R
DLLDLL
DLLDLL
ds022_01_121099
0
0
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0
Virtex™-E 1.8 V
Field Programmable Gate Arrays
Production Product Specification
Values stored in static memory cells control the configurable
logic elements and interconnect resources. These values
load into the memory cells on power-up, and can reload if
necessary to change the function of the device.
Input/Output Block
The Virtex-E IOB,
outputs that support a wide variety of I/O signalling stan-
dards, see
The three IOB storage elements function either as
edge-triggered D-type flip-flops or as level-sensitive latches.
Each IOB has a clock signal (CLK) shared by the three
flip-flops and independent clock enable signals for each
flip-flop.
Figure 2: Virtex-E Input/Output Block (IOB)
T
TCE
O
OCE
IQ
SR
CLK
ICE
I
Table
Q
D
CE
D
CE
SR
SR
SR
1.
CE
Q
Q
D
Figure
Programmable
Delay
2, features SelectI/O+ inputs and
OBUFT
IBUF
Vref
Keeper
Weak
ds022_02_091300
Module 2 of 4
PAD
1