XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 45

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Input termination techniques include the following.
•
•
These termination techniques can be applied in any combi-
nation. A generic example of each combination of termina-
tion methods appears in
Table 21: Guidelines for Max Number of Simultaneously Switching Outputs per Power/Ground Pair
DS022-2 (v2.8) January 16, 2006
Production Product Specification
LVTTL Slow Slew Rate, 2 mA drive
LVTTL Slow Slew Rate, 4 mA drive
LVTTL Slow Slew Rate, 6 mA drive
LVTTL Slow Slew Rate, 8 mA drive
LVTTL Slow Slew Rate, 12 mA drive
LVTTL Slow Slew Rate, 16 mA drive
LVTTL Slow Slew Rate, 24 mA drive
LVTTL Fast Slew Rate, 2 mA drive
LVTTL Fast Slew Rate, 4 mA drive
LVTTL Fast Slew Rate, 6 mA drive
LVTTL Fast Slew Rate, 8 mA drive
LVTTL Fast Slew Rate, 12 mA drive
LVTTL Fast Slew Rate, 16 mA drive
LVTTL Fast Slew Rate, 24 mA drive
LVCMOS
PCI
GTL
GTL+
Figure 43: Overview of Standard Input and Output
None
Parallel (Shunt)
Unterminated Output Driving
a Parallel Terminated Input
Series Terminated Output
R
Unterminated
Z=50
Z=50
Z=50
Termination Methods
V
V
REF
REF
V
TT
Figure
43.
Driving a Parallel Terminated Input
Series-Parallel Terminated Output
Series Terminated Output Driving
Double Parallel Terminated
a Parallel Terminated Input
Standard
V
TT
V
TT
Z=50
Z=50
Z=50
V
REF
V
V
REF
REF
V
TT
V
V
x133_07_111699
TT
TT
www.xilinx.com
Simultaneous Switching Guidelines
Ground bounce can occur with high-speed digital ICs when
multiple outputs change states simultaneously, causing
undesired transient behavior on an output, or in the internal
logic. This problem is also referred to as the Simultaneous
Switching Output (SSO) problem.
Ground bounce is primarily due to current changes in the
combined inductance of ground pins, bond wires, and
ground metallization. The IC internal ground level deviates
from the external system ground level for a short duration (a
few nanoseconds) after multiple outputs change state
simultaneously.
Ground bounce affects stable Low outputs and all inputs
because they interpret the incoming signal by comparing it
to the internal ground. If the ground bounce amplitude
exceeds the actual instantaneous noise margin, then a
non-changing input can be interpreted as a short pulse with
a polarity opposite to the ground bounce.
Table 21
simultaneously switching outputs allowed per output
power/ground pair to avoid the effects of ground bounce. See
Table 22
for each Virtex-E device and package combination.
Virtex™-E 1.8 V Field Programmable Gate Arrays
for the number of effective output power/ground pairs
provides guidelines for the maximum number of
BGA, CS, FGA
68
41
29
22
17
14
40
24
17
13
10
10
9
8
5
8
4
4
Package
HQ
49
31
22
17
12
10
29
18
13
10
7
7
6
4
7
6
4
4
Module 2 of 4
PQ, TQ
36
20
15
12
21
12
9
7
5
9
7
5
4
3
5
4
4
4
39