XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 143

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 18: FG456 — XCV200E and XCV300E
DS022-4 (v2.5) March 14, 2003
Production Product Specification
Bank
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Note 1: NC in the XCV200E device.
R
Pin Description
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Pin #
M14
M13
M12
M11
M10
C20
L14
L13
L12
L11
L10
K14
K13
K12
K11
K10
B21
A22
J14
J13
J12
J11
J10
M9
K9
C3
B2
A1
L9
J9
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1-800-255-7778
FG456 Differential Pin Pairs
Virtex-E devices have differential pin pairs that can also pro-
vide other functions when not used as a differential pair. A √
in the AO column indicates that the pin pair can be used as
an asynchronous output for all devices provided in this
package. Pairs with a note number in the AO column are
device dependent. They can have asynchronous outputs if
the pin pair are in the same CLB row and column in the
device. Numbers in this column refer to footnotes that indi-
cate which devices have pin pairs than can be asynchro-
nous outputs. The Other Functions column indicates
alternative function(s) not available when the pair is used as
a differential pair or differential clock.
Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E
Pair
10
11
12
13
14
15
16
17
0
1
2
3
0
1
2
3
4
5
6
7
8
9
Total Pairs: 119, Asynchronous Output Pairs: 69
Virtex™-E 1.8 V Field Programmable Gate Arrays
Bank
4
5
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Global Differential Clock
W12
Y11
A11
C11
E10
C10
B10
D11
D12
A13
B13
D13
Pin
D6
C7
B3
E6
E7
B6
B7
E9
B8
A8
P
IO LVDS
AA11
U12
D11
C12
C13
B11
F11
B11
B12
E12
Pin
D5
B4
A4
C6
A5
D7
E8
A7
C8
D9
C9
A9
N
AO
NA
NA
NA
NA
NA
NA
NA
NA
√
√
1
1
√
√
1
1
√
2
2
2
√
√
IO_LVDS_DLL
IO_DLL_L75N
IO_DLL_L13N
IO_DLL_L75P
IO_DLL_L13P
Functions
Module 4 of 4
Other
VREF
VREF
VREF
VREF
VREF
-
-
-
-
-
-
-
-
-
-
-
-
57